Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2000-04-17
2002-10-22
Peikari, B. James (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S134000, C711S136000
Reexamination Certificate
active
06470425
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to cache memory, and more particularly to cache memory in which frequently accessed data is not replaced.
In computer systems with cache memory, data which is stored in the cache memory is often replaced by new data. In a direct mapping protocol, a unique entry is provided for each index address. Therefore, there is a high probability that a plurality of different addresses are associated with the same entry (line) in cache memory. Alternatively, in the set associative protocol, a plurality of entries are provided for each index address. Even in this protocol, however, there is still a probability that access to different addresses results in the replacement of data existing in the cache memory. When a cache miss occurs and new data is stored in cache memory, an algorithm, such as the LRU (Least Recently Used) algorithm, is used to select an entry to be replaced.
As described above, when there is no free entry, a cache miss that occurs in conventional cache memory automatically brings new data therein and replaces existing data. This means that, in some cases, new data is stored in cache memory even if it is rarely used and that frequently used data is replaced by such rarely used data. Also, a casual access to data sometimes replaces frequently accessed data. A program that executes processing with a frequently used work area in cache memory may receive an interrupt during the processing. In this case, an entry in the work area may be rewritten.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide cache memory that inhibits frequently used data from being replaced and thereby to speed up overall system processing.
In one preferred embodiment, a cache memory according to the present invention has a plurality of entries, including a hit/miss counter checking a cache hit or a cache miss on each of the plurality of entries, and a write controller controlling an inhibition of a replacement of each of the plurality of entries based on a result of the checking made by the hit/miss counter.
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