Electrical computers and digital processing systems: processing – Processing control – Specialized instruction processing in support of testing,...
Reexamination Certificate
2008-05-27
2008-05-27
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Specialized instruction processing in support of testing,...
Reexamination Certificate
active
07380109
ABSTRACT:
An apparatus and method are provided for extending a microprocessor instruction set to allow for extended size addresses. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into an associated micro instruction sequence for execution by the microprocessor, where the extended instruction has an extended prefix and an extended prefix tag. Extended prefix specifies an extended address mode for an address calculation corresponding to an operation, where the extended address mode not otherwise provided for by instructions in an existing instruction set. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within the existing instruction set. The extended execution logic is coupled to the translation logic. The extended execution logic receives the associated micro instruction sequence, and performs the address calculation to generate an extended address according to the extended address mode.
REFERENCES:
patent: 3657705 (1972-04-01), Mekota et al.
patent: 4064554 (1977-12-01), Tubbs
patent: 4217638 (1980-08-01), Namimoto et al.
patent: 4547849 (1985-10-01), Louie et al.
patent: 5029069 (1991-07-01), Sakamura
patent: 5142679 (1992-08-01), Owaki et al.
patent: 5218712 (1993-06-01), Cutler et al.
patent: 5448744 (1995-09-01), Eifert et al.
patent: 5471595 (1995-11-01), Yagi et al.
patent: 5481684 (1996-01-01), Richter et al.
patent: 5687338 (1997-11-01), Boggs et al.
patent: 5751996 (1998-05-01), Glew et al.
patent: 5768574 (1998-06-01), Dutton et al.
patent: 5778220 (1998-07-01), Abramson et al.
patent: 5796973 (1998-08-01), Witt et al.
patent: 5822778 (1998-10-01), Dutton et al.
patent: 5826089 (1998-10-01), Ireton
patent: 5857103 (1999-01-01), Grove
patent: 5875342 (1999-02-01), Temple
patent: 5913049 (1999-06-01), Shiell et al.
patent: 5937199 (1999-08-01), Temple
patent: 5991872 (1999-11-01), Shiraishi et al.
patent: 6014735 (2000-01-01), Chennupaty et al.
patent: 6029222 (2000-02-01), Kamiya
patent: 6058472 (2000-05-01), Panwar et al.
patent: 6085312 (2000-07-01), Abdallah et al.
patent: 6157996 (2000-12-01), Christie et al.
patent: 6199155 (2001-03-01), Kishida et al.
patent: 6230259 (2001-05-01), Christie et al.
patent: 6317822 (2001-11-01), Padwekar
patent: 6351806 (2002-02-01), Wyland
patent: 6405305 (2002-06-01), Meier et al.
patent: 6434693 (2002-08-01), Senter et al.
patent: 6456891 (2002-09-01), Kranich et al.
patent: 6549999 (2003-04-01), Kishida et al.
patent: 6560694 (2003-05-01), McGrath et al.
patent: 6581154 (2003-06-01), Zaidi
patent: 6647488 (2003-11-01), Takeno et al.
patent: 6779103 (2004-08-01), Alexander, III et al.
patent: 6823414 (2004-11-01), Radhakrishna
patent: 6883053 (2005-04-01), Shinagawa et al.
patent: 2001/0013870 (2001-08-01), Pentkovski et al.
patent: 2002/0194457 (2002-12-01), Akkary
patent: 2003/0159020 (2003-08-01), Henry et al.
patent: 2003/0172252 (2003-09-01), Henry et al.
patent: 2003/0188130 (2003-10-01), Henry et al.
patent: 2005/0102492 (2005-05-01), Henry et al.
patent: 2005/0188179 (2005-08-01), Henry et al.
patent: 1431584 (2003-07-01), None
patent: 0550289 (1993-07-01), None
patent: 0942359 (1999-09-01), None
patent: 0947919 (1999-10-01), None
patent: WO-9722922 (1997-06-01), None
Intel Architecture Software Developer's Manual, vol. 2: Instruction Set Reference, 1999, pp. 2-1 to 2-4, 3-332, 3-353 and B-25.
Paap et al, “Power PC™: A Performance Architecture,” COMPCON Spring '93, Digest of Papers, San Francisco, CA, IEEE Computer Society, Feb. 22, 1993, pp. 104-108.
Silberman et al.An Architectural Framework for Supporting Heterogeneous Instruction-Set Architectures. Computer, IEEE Computer Society, Long Beach, CA. US vol. 26, No. 6, Jun. 1, 1993. pp. 39-56. ISSN: 0018-0162.
Patterson & Hennessy. “Computer Organization and Design: The Hardware/Software Interface.” 1998. Morgan Kaufmann Publishers, Inc. Second Edition. pp. 177-178, 297.
Dobb. “Microprocessor Resources.” 2000. http://web.archive.org/web/20000118231610 http://x86.org/secrets/opcodes/lcebp.htm.
Henry G. Glenn
Hooker Rodney E.
Parks Terry
Chan Eddie
Fennema Robert E
Huffman James W.
Huffman Richard K.
IP-First LLC
LandOfFree
Apparatus and method for providing extended address modes in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for providing extended address modes in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for providing extended address modes in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2773040