Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2002-04-11
2003-11-25
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S093000, C327S407000, C327S099000, C327S298000, C713S501000
Reexamination Certificate
active
06653867
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of digital circuits. More particularly, the invention relates to an apparatus and method for providing a smooth transition between two clock signals of different frequencies that drive a digital circuit.
BACKGROUND OF THE INVENTION
Clock pulses drive digital circuits. In many cases, digital circuits utilize more than one clock source. Because the clock frequency of each clock may differ, there may be faster clocks and slower clocks that drive the same digital circuit. When more than one clock source drives the same digital circuit, a special circuit is required to select which clock is to drive the digital circuit. In switching between two clock sources, a glitch on the output clock may be created. A glitch may be in the form of a short pulse (also referred to as a spike). A glitch sometimes leads to faulty behavior of the digital circuit if the digital circuit contains elements that receive the clock signal (e.g., flip-flop circuits) The faulty behavior can cause a reduction in the performance of the digital circuit, especially in digital circuits that require high levels of accuracy.
U.S. Pat. No. 5,790,609 discloses a circuit that switches between a plurality of clock sources to provide one clock at a time. The circuit comprises a clock acquisition subsystem for a data processing system. The clock acquisition subsystem comprises an interlocked clock multiplexer for acquiring a clock source which is provided as the clock signal to the data processing system. The multiplexer has at least two inputs for clock source signals. A control register specifies the clock source to be selected by the multiplexer. The multiplexer has an interlocked synchronizer on each clock signal input so that when the multiplexer is switched, the output clock signal shifts cleanly from a first clock source to a second clock source without glitches or runt pulses. However, the switch delay lasts for two periods of the output clock, plus two periods of the selected clock. This period adds a delay that equals the period of the slowest clock in the worst case, thus reducing the accuracy of the system, particularly if the circuit is a high resolution timer.
U.S. Pat. No. 5,604,452 discloses a circuit that switches between two clock signals to produce an output clock signal without a glitch or short pulse. The circuit comprise a three-input multiplexer controlled by a modified two-bit state machine. The state machine includes flip-flop memories that are driven by two different clocks. The state machine output is used to control the three-input multiplexer, selecting between the first clock, the second clock and an intermediate high level signal during transition. The intermediate high level signal bridges the gap between pulses, eliminating any short pulse glitches. However, the switching is done after one edge of the first clock and one edge of the second clock. The total delay is the sum of the delay of the two clocks, which will always take the time of the slowest clock. This feature increases delays and reduces the accuracy of the system, particularly if the output clock drive is a high resolution clock drive. Moreover, the switching is done in three stages. The first stage occurs at the rising edge of the output clock (i.e., the point in time in which pulse changes the voltage level from low voltage to high voltage). The second stage occurs when the output goes to a high level (logic level “1”) for a. period of time. The third stage occurs at the rising edge of the selected clock.
U.S. Pat. No. 5,652,536 discloses a clock switching circuit that is responsive to at least one clock select signal. The clock switching circuit switches between a plurality of clock signals while minimizing transients generated during the switching. The circuit comprises at least one flip-flop that receives a corresponding at least one clock select signal. The circuit also comprises a plurality of flip-flops that individually receive an output of a corresponding one of the at least one flip-flop, and an inverted version of a corresponding one of the clock signals. The circuit also comprises a plurality. of AND gates that individually receive the output of a corresponding one of the at least one flip-flop, the output of a corresponding one of the plurality of flip-flops, and a corresponding one of the plurality of clock signals, and an OR gate that receives the outputs of the AND gates so that the selected one of the plurality of clock signals is provided at an output of the OR gate, and fed back to an inverted clock input of the at least one flip-flop. Timing of the clock switching circuit is such that a first clock signal is provided to the circuit until a first falling edge (i.e., the moment in time where the pulse changes its voltage level from high to low) of-the first clock signal occurs following an indication to change clock signals.
A second clock signal is provided to the circuit after a first falling edge of the second clock signal occurs, following the first falling edge of the first clock signal, following the indication to change clock signals. The switching between the clocks starts by turning off the output clock, then, after a delay of up to one period of the selected clock, turning on the output, with the new selected clock as the output clock. However, if the selected clock is the slower clock, then there will be a delay of up to one period of the slowest clock. This adds a delay that is equal to the period of the slowest clock, thus reducing the accuracy of the system, particularly if the circuit is a high resolution timer.
A glitch may occur where a digital system has one reference clock source that generates several other clocks with lower frequencies and at least one of the generated clocks has a frequency that is equal to the reference clock frequency divided by an odd number (e.g.,
3
,
5
,
7
, etc.). In such cases the odd number generated clock may switch at different edges of the reference clock, such that its rising edge will be after the rising edge of the reference clock and its falling edge will be after the falling edge of the reference clock.
All the apparatus and methods described above have not yet provided a satisfactory solution to the problem of operating a digital system with two clock sources having different frequencies.
It would be desirable to have an apparatus and method for preventing glitches that occur on an output signal during the process of switching between two clock sources in a digital circuit where one clock source is slower than the other clock source by an odd ratio.
It would be desirable to have an apparatus and method for reducing delay when switching between two clock sources in a digital circuit.
It would also be desirable to have an apparatus and method for increasing the accuracy of a digital system when switching between two clock sources, particularly when the digital system is to be used in a high resolution timer or counter.
It would also be desirable to have an apparatus and method for preventing delay that occurs during the process of switching between two clock sources, when one clock source is considerably faster than the other clock source.
SUMMARY OF THE INVENTION
The present invention is directed to an apparatus and method for providing a smooth transition when switching between two clock sources in a digital circuit where one clock source is slower than the other clock source.
An advantageous embodiment of the present invention comprises circuitry for generating a pulse that indicates when the logic levels of the first and the second clock signals are similar and when they are different. The rising/falling edges of the pulse are synchronized with the rising/falling edges of the first clock signal. When a change in a logic level of a command signal for switching between the clock signals is detected, a first time period is identified in which the pulse is in a logic level that indicates that the logic levels of the first and second clock signals are different. The transition between the
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