Semiconductor device

Details Semiconductor device Semiconductor device

2001-07-10

2003-11-25

Flynn, Nathan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S773000, C257S734000, C257S382000, C257S908000

Reexamination Certificate

active

06653739

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a contact hole defined by a self-aligning manner.
2. Description of the Background Art
With an improvement in integration of a semiconductor device and the scaling-down of a memory cell, difficulties have recently been encountered in defining a contact between adjacent wirings without developing a short circuit in wiring. A technique called a self-aligning manner has heretofore been used as one method for defining a contact hole while preventing a short circuit developed in wiring.
FIGS. 1A through 1F
respectively show a series of cross-sectional views for describing a conventional method of defining a contact hole by using a self-aligning manner. According to the conventional method, an interlayer oxide film
12
is first deposited on a semiconductor substrate
10
as shown in
FIG. 1A. A
silicon film
14
is deposited on the interlayer oxide film
12
and a nitride film
16
for protecting the silicon film
14
is further deposited thereon.
Next, the silicon film
14
and the nitride film
16
are patterned in desired wiring form as shown in FIG.
1
B.
Afterwards, sidewalls
18
for protecting the side faces of each silicon film
14
are formed by a nitride film as shown in FIG.
1
C. Each silicon film
14
patterned in wiring form is brought to a state of being covered with the nitride film at this stage.
After the sidewalls
18
have been formed, an interlayer oxide film
20
is deposited over the entire surface of a semiconductor wafer as shown in FIG.
1
D. Next, a predetermined heat treatment is carried out to enhance the embedding characteristics and flatness of the interlayer oxide film
20
.
As shown in
FIG. 1E
, a photoresist
22
is patterned onto the interlayer oxide film
20
. Oxide-film etching for defining a contact hole
24
is executed with the photoresist
22
as a mask. This etching is carried out under a condition for removing an oxide film at a higher selectivity than that for the nitride film. Since, in this case, each of the nitride film
16
and sidewalls
18
functions as a stopper film for stopping the progress of the etching, the contact hole
24
can be defined up to the semiconductor substrate
10
without exposing each wiring to the inside of the contact hole
24
even when a opening of the photoresist
22
is wider than the interval between the wirings. A technique for defining the contact hole in place on a self-alignment basis in this way is called a “self-aligning manner”.
The photoresist
22
is removed after the contact hole
24
has been defined. A silicon film is deposited over the entire surface of a semiconductor wafer so that the contact hole
24
is filled with silicon. The so-deposited silicon is patterned in desired shapes, so that such a contact plug
26
and a wiring
28
as shown in
FIG. 1F
are formed.
In the aforementioned conventional method, the etching for defining the contact hole
24
is carried out under the circumstances in which the side faces of each silicon film
14
patterned in wiring form have been covered with the sidewalls
18
. In this case, the width of the contact hole
24
in the vicinity of a lower end thereof becomes narrower than the interval defined between the adjacent two sidewalls
18
. According to the etching for defining the contact hole
24
by which an oxide film is anisotropically etched at a higher selectivity than that for the nitride film, the interlayer oxide film
12
located below the sidewalls
18
is etched in tapered form.
As a result, the diameter of the bottom of the contact hole
24
becomes drastically smaller than the interval defined between the adjacent silicon films
14
, i.e., the interval defined between the wirings. Therefore, the conventional method is apt to cause problems such as an increase in contact resistance, degradation of drive capability of a transistor.
As a technique for solving the above problems, it can be used illustratively a method in which the contact hole
24
is defined by dry etching, and thereafter HF-system wet etching or the like is carried out to thereby retreat the interlayer oxide film
12
.
However, as shown in
FIG. 2
, such wet etching may cause exposed portions
30
formed at parts of the bottoms of silicon films
14
so as to be exposed inside the contact hole
24
. In this configuration, a short circuit would be developed between each silicon film
14
and the contact plug
26
which is formed inside the contact hole
24
.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above problems. An object thereof is to provide a semiconductor device having a contact hole whose bottom is scaled up, and a structure suited to prevent a short circuit from arising between a wiring and a contact plug.
The above objects of the present invention are achieved by a semiconductor device described below. The semiconductor device includes a contact hole defined between adjacent two wirings by a self-aligning manner. A contact plug is formed in the contact hole. A substrate layer is provided so as to be conductive to the bottom face of the contact plug. An interlayer oxide film is formed on the substrate layer. A lower insulating film formed of a nitride based insulating film is provided so as to cover the entire surface of the interlayer oxide film except for the contact hole portion. The two wirings are formed on the lower insulating film with the contact hole interposed therebetween. An upper insulating film formed of a nitride based insulating film is provided with the same width as the each wiring so as to cover the upper surface of the each wiring. The semiconductor device also includes sidewalls formed of a nitride based insulating film so as to cover the side faces of the each wiring and the side faces of the upper insulating film. The contact hole has an enlarged portion formed in the same layer as the interlayer oxide film, which has a diameter larger than an interval defined between the two wirings.
The above objects of the present invention are also achieved by a semiconductor device described below. The semiconductor device includes a contact hole defined between adjacent two wirings by a self-aligning manner. A contact plug is formed in the contact hole. A substrate layer is provided so as to be conductive to the bottom face of the contact plug. An interlayer oxide film is formed on the substrate layer. The two wirings are formed in a layer above the interlayer oxide film with the contact hole interposed therebetween. A lower insulating film formed of a nitride based insulating film is provided between the interlayer oxide film and the each wiring with the same width as the each wiring. An upper insulating film formed of a nitride based insulating film is provided so as to cover the upper surface of the each wiring with the same width as the each wiring. The semiconductor device also includes sidewalls formed of a nitride based insulating film so as to cover the side faces of the each wiring and the side faces of the upper and lower insulating films. The contact hole has a diameter larger than an interval defined between the two wirings within the same layer as the interlayer oxide film. The bottom face of the each sidewall is shifted toward the substrate layer by a predetermined length as compared with the bottom face of the lower insulating film.
The above objects of the present invention are further achieved by a semiconductor device described below. The semiconductor device includes a contact hole defined between adjacent two wirings by a self-aligning manner. A contact plug is formed in the contact hole. A substrate layer is provided so as to be conductive to the bottom face of the contact plug. An interlayer oxide film is formed on the substrate layer The two wirings are formed on the interlayer oxide film with the contact hole interposed therebetween. An upper insulating film formed of a nitride based insulating film is provided so as to cover the upper

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