Electronic digital logic circuitry – Multifunctional or programmable
Reexamination Certificate
2003-01-08
2004-08-10
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
C326S040000, C365S185010
Reexamination Certificate
active
06774668
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to providing configuration information to an integrated circuit, and more particularly to a method and apparatus for providing configuration information to a selectable function prior to a complete initialization of the integrated circuit.
BACKGROUND
Today's digital logic based electronic systems can have a logic complexity implemented in hardware comparable to the logic employed in software systems developed only a few years ago. Many such systems have achieved this complexity by relying on complex programmable logic devices (CPLD) to perform data processing, manipulation, and control.
Because CPLDs are re-programmable, designers can easily and very inexpensively change their designs. This allows designers to optimize their designs and continue to add new features, thus enhancing their products.
CPLDs offer a high level of integration, including a large number of system gates per unit area, and are available in very small packages. This provides a good solution for designers of products that must fit into small enclosures or that have a limited amount of circuit board space to implement a particular logic design.
CPLDs typically include an array of logic function generators or configurable logic elements, input/output ports, and a matrix of interconnect lines. The matrix of interconnect lines generally surrounds the configurable logic elements and connects logic data signals among the various configurable logic elements and between the configurable logic elements and the input/output ports.
A CPLD is re-programmable because the logical relationship between its inputs and outputs is controlled by configuration information contained in a configuration memory associated with the CPLD. The configuration memory is comprised of memory cells that define an interconnection of logic elements, including connection of outputs of some elements to the inputs of other logical elements. It is advantageous to store such configuration information in nonvolatile memory, such as electrically erasable programmable read only memory (EEPROM), or flash memory, because configuration information stored in nonvolatile memory persists even after electrical power is disconnected from a particular device.
In a conventional CPLD, values of particular EEPROM cells are provided directly to logic components within the CPLD. In order to provide the value of a particular state of a particular EEPROM memory cell, a sense amplifier is required to determine the state of the stored bit of information from within the EEPROM. Unfortunately, the sense amplifiers associated with EEPROM memory consume a significant amount of power when they are enabled. Accordingly, while it is possible to use a purely EEPROM based CPLD, such devices have the serious shortcoming of consuming significant amounts of power, for example as much as 30-40 mA or more at about 2.5 V.
Volatile memory, such as SRAM, can also be used to provide interconnection information to the logic resources associated with a CPLD. For example, SRAM-based CPLDs provide logical configuration information to a CPLD without the sense amplifiers required for use in connection with EEPROMs. In contrast to EEPROMs, SRAM cells consume relatively little power while enabled and operating. Accordingly, reading from SRAM cells consumes relatively little power in comparison to reading from EEPROM cells. To address this power problem and other problems, CPLDS have been designed that employ both volatile and nonvolatile memory. Such CPLDs include the CoolRunner II family of CPLDs available from Xilinx, Inc. of San Jose, Calif. In these CPLDS, configuration information is persistently stored in EEPROM and transferred to SRAM upon initialization of the CPLD. This transfer or initialization process can take from approximately 20 &mgr;s to approximately 100 &mgr;s, and, in some cases, can take much longer, for example up to 1 second. Once the configuration information has been transferred from the EEPROMs to the SRAMs, the EEPROMs and associated sense amplifiers can be disabled, thereby conserving a significant amount of power.
CPLDs that employ both volatile and nonvolatile memory, however, suffer from the drawback that they do not operate until all of the configuration information has been transferred from the nonvolatile memory to the volatile memory. During this transfer time, some CPLDs place all of the I/O pins into a high impedance state to avoid adverse affects to the system in which the CPLD is operating.
In some CPLD target systems, particularly target systems having multiple system voltages, it can take a significant period of time for the target system to reach an initial stable system-power level. As described above, it takes a significant amount of time for the nonvolatile memory to be transferred to the volatile memory (more than about 20 &mgr;s). Furthermore, the CPLD should not begin operation (including nonvolatile to volatile memory transfer) until the CPLD has stable system power and until the target system is otherwise ready for the CPLD to begin operation. Unfortunately, the CPLD cannot use a general purpose I/O pin, for example, to receive a status indication that power is stable and the target system is ready for the CPLD to begin operation if that pin is in a high impedance state. The fact that the CPLD should not begin operation until the target system is ready combined with the fact that the CPLD cannot determine whether the target system is ready without first completing initialization can be characterized as a chicken-and-egg problem.
Accordingly, it would be beneficial to provide, for example, a “hold off” input pin on a CPLD to tell the CPLD to wait for a stable, relatively noise-free system power level before beginning initialization of the SRAM, and thereby solve the chicken-and-egg problem. This could be accomplished using a dedicated pin on a CPLD; however, it would be advantageous to preserve as many I/O pins in a particular package associated with a CPLD for actual use as logical inputs and outputs in system design rather than to waste a pin for a dedicated “hold off” function, for example, that is not needed in a particular application.
Accordingly, there is a need for methods and systems that overcome the problems associated with CPLDs, without requiring dedicated pins.
SUMMARY OF THE INVENTION
A programmable integrated circuit is provided, including one or more nonvolatile memory cells programmed to represent configuration bits associated with a special purpose function or functions. Corresponding volatile memory cells are associated with the nonvolatile memory cells, and in the preferred embodiment, after initialization of the integrated circuit, the volatile memory cells take on the data values stored in the nonvolatile memory cells. The integrated circuit includes a logic gate for logically combining outputs of the volatile and nonvolatile memory cells for selectively enabling the special purpose function or functions, even before the volatile memory cells are initialized. In this way, the predetermined function can be executed prior to a complete initialization of the integrated circuit.
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Brown Scott R.
Liu Justin
Nguyen Linh Van
Tokar Michael
Xilinx , Inc.
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