Apparatus and method for operably connecting a processor cache a

Details Apparatus and method for operably connecting a processor cache a Apparatus and method for operably connecting a processor cache a

1997-05-08

1999-11-16

Thai, Tuan V.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711102, 711104, 711147, 712 34, 712 35, G06F 1200, G06F 1300

Patent

active

059875682

ABSTRACT:
A peripheral module capable of interaction with a host system comprises a digital signal processor (DSP), a cache controller, and minimal or no resident memory for initial storage of instructions and data. The peripheral module utilizes the memory resources (e.g., ROM and RAM) of a host system. The cache controller interfaces to the DSP and provides an instruction and data stream, upon request, from a resident cache. A bus interface unit arbitrates access to the host system via a host bus for access to host system resources by the cache controller for extracting DSP information (e.g., instructions and data) from the host system for utilization by the DSP within the peripheral module. The cache controller and cache thereby provide the instruction and data stream as required by the DSP for digital signal processing applications and relieve the need for resident storage within the peripheral module.

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