Apparatus and method for noise reduction in DRAM

Details Apparatus and method for noise reduction in DRAM Apparatus and method for noise reduction in DRAM

1998-10-15

2000-11-14

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Noise suppression

365203, G11C 700

Patent

active

061479179

ABSTRACT:
An apparatus (and method) is provided that reduces noise in an embedded DRAM caused by noise in the Vdd supply. A circuit switches or decouples the bit line precharge voltage supply from the memory array to reduce noise in the memory array at time of bit line sensing. In addition, another circuit is utilized to switch or decouple the memory cell plate voltage supply from the memory array to reduce noise in the memory array at the time of bit line sensing. The circuit(s) includes a switch to perform the decoupling, or alternatively, include a switch coupled in parallel with a high impedance.

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