Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2008-04-08
2008-04-08
Rose, Kiesha L. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S365000
Reexamination Certificate
active
10844197
ABSTRACT:
A multiple-gate transistor has an active region with a side that forms an interior angle with the base of the active region of less than 80°. A process for fabricating a FinFET includes the steps of etching a silicon-on-insulator wafer to form an active region, including the source, channel, and drain, with vertically angled sidewalls.
REFERENCES:
patent: 6413802 (2002-07-01), Hu et al.
patent: 2004/0150029 (2004-08-01), Lee
patent: 2005/0040444 (2005-02-01), Cohen
Wu, Xusheng et al. , “Impact of Non-Vertical Sidewall on Sub-50nm FinFET,” IEEE, 2003.
King, T-J., et al., “Advanced Materials and Processes for Nanometer-Scale FinFETs,” University of California, Berkeley, date unknown, U.S.A.
Yu, B., et al., “FinFET Scaling to 10nm Gate Length,” IEEE, 2002.
Kedzierski, J., et al., “A 20 nm Gate-Length Ultra-Thin Body p-MOSFET with Silicide Source/Drain,” Superlattices and Microstructures, vol. 28, No. 5/6, 2000, pp. 445-452.
Krishnan, M.S., et al., “MOSFETs with 9 to 13 a Thick Gate Oxides,” IEEE, 1999.
Zhang, S., et al., “A Novel Sub-50 nm Poly-Si Gate Patterning Technology,” IEEE, 2001, pp. 841-843.
Barkhordarian, V., “Power MOSFET Basics,” www.irf.com/technical-info/appnotes/mosfet.pdf, International Rectifier, date unknown.
American Microsemiconductor, “MOSFETS,” http://www.americanmicrosemi.com/tutorials/mosfets.htm.
Chang, L., et al., “Moore's Law Lives On: Ultra-Thin Body SOI and FinFET CMOS Transistors Look to Continue Moore's Law for Many Years to Come,” IEEE Circuits & Devices Magazine, Jan. 2003, pp. 35-42.
Tang, S.H., et al., “FinFET—A Quasi-Planar Double Gate MOSFET,” ISSCC 2001 / Session 7 / Technology Directions: Advanced Technologies / 7.4, 2001 IEEE International Solid-State Circuits Conference, Feb. 6, 2001.
Huang, X., et al., “Sub-50 nm P-Channel FinFET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Lindert, N., et al., “Sub-60-nm Quasi-Planar FinFETs Fabricated Using a Simplified Process,” IEEE Electron Device Letters, vol. 22, No. 10, Oct. 2001, pp. 487-489.
Geppert, L., “The Amazing Vanishing Transistor Act,” IEEE Spectrum, Oct. 2002, pp. 28-33.
Rose Kiesha L.
Slater & Matsil L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
LandOfFree
Apparatus and method for multiple-gate semiconductor device... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for multiple-gate semiconductor device..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for multiple-gate semiconductor device... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3917647