Apparatus and method for minimizing diffusion in stacked...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S253000, C438S396000, C438S658000, C438S775000, C438S922000

Reexamination Certificate

active

06228701

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The invention relates generally to methods and apparatus for integrating capacitors into integrated circuits. More particularly, the invention relates to methods and apparatus for reducing the amount of contaminants which migrate from a high dielectric layer of a stacked capacitor into silicon during processing of the stacked capacitor, and for reducing contaminants which migrate from silicon into the high dielectric layer.
2. Description of the Relevant Art
As the demand for integrated circuits, such as dynamic random access memory (DRAM) integrated circuits, increases, the need for efficiently produced integrated circuits is also increasing. Producing integrated circuits in such a way that the integrity of the integrated process may be protected throughout the fabrication process increases the overall throughput of the integrated circuits.
Many integrated circuits include capacitors, such as stacked capacitors.
FIG. 1
is a diagrammatic cross-sectional representation of a stacked capacitor formed on an integrated circuit. A stacked capacitor structure
104
is typically included as part of an integrated circuit, e.g., a DRAM integrated circuit. Stacked capacitor structure
104
is formed over a substrate
106
of the integrated circuit. Substrate
106
is generally formed from silicon, and includes a junction region
107
. Junction region
107
is generally a doped region in substrate
106
that is the source or the drain element of a FET. Substrate
106
may also include various other layers associated with the formation of an integrated circuit. By way of example, substrate
106
may include various insulating layers and conducting layers.
A polycrystalline silicon plug
110
overlays substrate
106
. In general, polycrystalline silicon plug
110
may be doped using a dopant such as boron, phosphorous, or arsenic. A silicon dioxide layer
112
is located over substrate
106
, and is arranged around polycrystalline silicon plug
110
.
A bottom electrode
116
is disposed over polycrystalline silicon plug
110
. An adhesion layer
114
is disposed between bottom electrode
116
and polysilicon plug
110
essentially to hold bottom electrode
116
in place. As shown, adhesion layer
114
also partially overlays silicon dioxide layer
112
.
A layer of material with a relatively high dielectric constant
118
, e.g., a “high dielectric layer,” is arranged over bottom electrode
116
and portions of silicon dioxide layer
112
. A top electrode
120
is conformally disposed over high dielectric layer
118
. High dielectric layer
118
is generally arranged to insulate bottom electrode
116
from top electrode
120
. Further, high dielectric layer
118
may increase charge holding capability of capacitor structure
104
and, hence, improve storage device operation.
When a capacitor, e.g., a stacked capacitor, is incorporated into an integrated circuit, materials in the high dielectric layer of the capacitor are likely to vertically diffuse into an underlying junction area during annealing processes which generally occur at temperatures of greater than approximately 800 degrees Centigrade. Materials in the high dielectric layer which may diffuse into the underlying junction area include, but are not limited to, materials such as lead zirconium titanate (PZT), barium strontium titanate (BST), and strontium bismuth titanate (SBT). When such materials diffuse out of the high dielectric layer, the integrity of the underlying junction area may be compromised. By way of example, leakage may occur in the junction area.
During annealing processes, such as those used to achieve desired dielectric properties, silicon from a polycrystalline silicon plug that is part of an overall stacked capacitor structure may diffuse vertically, as well as laterally, from the polycrystalline silicon plug into the high dielectric layer. When silicon diffuses into the high dielectric layer, compounds such as silicon oxide (SiO
x
) may form, particularly at the interface between the high dielectric layer and the electrodes. Since silicon oxides are generally relatively high in resistance, and, further, have low dielectric constants, the formation of silicon oxides in a stacked capacitor may significantly degrade the overall dielectric properties of the capacitor.
Further, when the polycrystalline silicon plug is formed from doped polycrystalline silicon, dopants may diffuse from the polysilicon plug into the electrodes and the high dielectric layer, thereby altering the properties of the high dielectric layer. It has been observed that the amount of dopant which diffuses out of the doped polycrystalline silicon plug during annealing processes is greater than approximately 50 percent, as for example in the range of approximately 50 percent to approximately 70 percent, of the total amount of dopant in the doped polycrystalline silicon plug.
Reducing the thermal budget of an integrated circuit fabrication process, while generally effective in reducing diffusion within a stacked capacitor, often proves to be undesirable. For example, when the thermal budget is reduced, high temperature steps, i.e., steps which occur at temperatures of greater than approximately 800 degrees Centigrade, associated with the fabrication of an overall integrated circuit may be shortened. Such steps include reflowing dielectrics, and activating doped junctions, for example. Further, for DRAMS, reducing the number of dislocations which may be healed significantly compromises the retention time associated with the DRAM by increasing device leakage. Retention time is the time a DRAM cell retains its stored charge, and is limited by the rate that the stored charge leaks away.
Therefore, what is desired is a method and an apparatus for reducing contaminant outdiffusion and silicon diffusion in a stacked capacitor without compromising the integrity or the performance of an integrated circuit which includes the stacked capacitor.
SUMMARY OF THE INVENTION
Methods and apparatus for fabricating stacked capacitor structures, which include barrier layers, within an integrated circuit, are disclosed. According to one aspect of the present invention, a method for minimizing outdiffusion within an integrated circuit includes forming a source/drain region or a junction region on a substrate, and further forming a silicon plug over a source or drain region. A silicon dioxide layer is formed over the source/drain, and is then etched to form openings for the silicon plug. Once the silicon plug is formed, a first barrier film is formed over the silicon plug, a dielectric layer is formed over the silicon dioxide layer, and a first electrode is formed, including an adhesion layer. Finally, a second electrode is formed over the dielectric layer
In one embodiment, forming the first barrier film includes forming a first oxide layer over the silicon plug, nitridizing the first oxide layer, and etching the nitridized first oxide layer. In such an embodiment, etching the nitridized first oxide layer exposes nitride at grain boundaries of the silicon plug. In another embodiment, forming the first barrier film includes performing a chemical vapor deposition to form an oxynitride film over the silicon plug and etching the oxynitride film to expose nitride at grain boundaries, especially grain boundaries near the top surface, of the silicon.
According to another aspect of the present invention, a stacked capacitor arrangement on an integrated circuit chip which has a junction region includes a silicon plug disposed over a portion of the junction region. A silicon dioxide layer is disposed over the junction region and at least partially around the silicon plug, and a first barrier film is formed over the silicon plug. A first electrode is secured over the silicon plug by an adhesion layer, and a layer of high dielectric material is disposed over the first electrode. In one embodiment, the silicon plug is a polysilicon plug, and the first barrier film includes nitride. In another embodiment, the layer of high dielectric

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Apparatus and method for minimizing diffusion in stacked... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus and method for minimizing diffusion in stacked..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for minimizing diffusion in stacked... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2438563

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.