Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-01-17
2006-01-17
Chase, Shelly (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S786000
Reexamination Certificate
active
06988234
ABSTRACT:
An apparatus for memory sharing between an interleaver and a deinterleaver in a turbo decoder is disclosed. A memory writes therein data obtained by interleaving data decoded by a decoder and writes therein data obtained by deinterleaving the data decoded by the decoder, in response to a control signal. A controller reads the stored interleaved data for a delay time of the decoder, generates a first control signal for writing the interleaved signal in the memory after a lapse of the delay time, writes the deinterleaved data in the memory for the delay time, and generates a second control signal for reading the stored deinterleaved data after a lapse of the delay time.
REFERENCES:
patent: 6392572 (2002-05-01), Shiu et al.
patent: 6574766 (2003-06-01), Obuchi et al.
patent: 6732327 (2004-05-01), Heinila
Chase Shelly
Dilworth & Barrese LLP
Samsung Electronics Co,. Ltd.
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