Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-06-04
2003-11-11
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185290, C365S185220, C365S185240, C365S185260, C365S185180
Reexamination Certificate
active
06646919
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to quality control testing of non-volatile memory cells. More particularly, the invention relates to margin testing of single polysilicon process EEPROM cells.
Non-volatile memory cells include EPROM, Flash and EEPROM cells. EPROM and Flash cells are programmed by hot electron injection and erased by exposure to UV radiation and by Fowler-Nordheim tunneling, respectively. However, EEPROM cells are both electrically programmed and electrically erased by Fowler-Nordheim tunneling. Unlike EPROM and Flash cells, the threshold voltage associated with a discharged EEPROM cell is negative because electrons beyond the neutral state may be removed from the floating gate. This electron removal gives the floating gate a net positive charge. As described below, this difference can present a challenge to effective margin testing, particularly of the erase margin, in certain types of EEPROMs.
EEPROM cells may have a variety of configurations. In particular, EEPROMs may be formed from single or double polysilicon processes. A double polysilicon process EEPROM has a polysilicon control gate capacitively coupled to its floating gate. A single polysilicon process EEPROM does not have a polysilicon control gate, but instead has a second heavily doped diffusion implant in the cell's substrate which is capacitively coupled to its floating gate. Margin testing of single polysilicon (“single poly”) EEPROMs are the focus of this invention.
A dual row line single polysilicon EEPROM cell
30
is shown in FIG.
1
A. The cell includes a single polysilicon floating gate structure
32
which performs three functions. At a first end, a tunnel extension
34
of floating gate
32
acts as an electrode in the two terminal device used for tunneling electrons from a heavily doped N
+
implant
35
(also referred to as a programming Memory Diffusion or MD) through a tunnel oxide
36
(often about 80 Å thick) onto floating gate structure
32
. At the other end of this floating gate, a wide area plate
38
is employed as one electrode of a capacitor enabling the floating gate
32
to be raised to a high voltage (e.g., about 6 to 11 volts) by capacitively coupling a programming voltage (e.g., about 9 to 13 volts) from a second electrode
40
(heavily doped N+ silicon, referred to herein as a control gate memory diffusion) through an oxide
42
(often about 180 Å thick). Between these two ends is a section of polysilicon that forms the gate
44
of a read transistor (N
2
).
The read transistor (N
2
) is connected in series with a word line transistor (N
1
) having a gate
46
forming part of a word line (also referred to as a row line)
47
. The read and word line transistors separate a sense amp negative (−) input
48
(a source line) from a sense amp positive (+) input
50
(a drain line). Charging the floating gate
32
by tunneling electrons onto it (through tunnel oxide
36
) raises the threshold voltage of the read transistor (EEPROM cell
30
is programmed). This shuts off the channel between the sense amp inputs, even when the adjacent word line transistor is turned on. Tunneling electrons off the floating gate
32
reduces the read transistor threshold voltage to negative values, effectively turning this device on (EEPROM cell
30
is erased). The word line transistor in series then controls the signal path between the two sense amp inputs
48
and
50
.
The EEPROM cell is programmed or erased by charging or discharging, respectively, the floating gate
32
. In order to tunnel electrons onto floating gate
32
, a high voltage must be applied to the control gate memory diffusion
40
. At the same time, the write column
56
is grounded and the write column transistor (N
3
) is turned on by, for example, selecting the second row line 31 of the dual row line cell with, for example, 5 volts. The sense amp (−) input 48 can be biased from about 5 volts to a high voltage to assist tunneling electrons onto the floating gate
32
. The voltage on the control gate memory diffusion
40
is capacitively coupled to the floating gate
32
as is the sense amp (−) input
48
voltage. The resulting positive voltage on floating gate
32
is sufficient to cause tunneling onto floating gate
32
through the tunnel oxide
36
where it intersects the floating gate (the tunnel oxide window
36
a
(shaded)), thereby programming the EEPROM cell
30
.
In order to tunnel electrons off floating gate
32
, a high voltage must be applied to memory diffusion
35
while ground is applied to the second heavily doped N+ implant (control gate memory diffusion)
40
which underlies and is capacitively coupled to the wide area plate
38
. During this process, ground is also applied to sense amp (−) input
48
. The application of high voltage to memory diffusion
35
is accomplished through a write column
56
and a write column select transistor (N
3
) including (i) a diffusion region
54
conductively connected to write column
56
for data input, (ii) a source/drain diffusion
58
electrically connected to memory diffusion
35
, and (iii) a gate electrode
60
, which is part of row line
31
. When a sufficient potential is applied to the gate
60
of the write column select transistor through row line
31
while a write signal is applied through write column
56
, electrons can tunnel off of the floating gate
32
to erase the EEPROM cell.
A further description of a typical EEPROM cell and its functional elements is available the publication “EPM7032 Process, Assembly, and Reliability Information Package” available from Altera Corporation of San Jose Calif. That document is incorporated herein by reference for all purposes.
In order for an MOS transistor to conduct, the voltage on its gate must overcome (be greater than) the transistor's threshold voltage (V
th
). Generally, the threshold voltage is that gate voltage required to create an inversion layer in the transistor's channel so that it conducts, and is a function of the design and process criteria for the cell. When the MOS transistor is a programmable transistor, such as an EEPROM, there are two gates: The floating gate and the control gate. Such a cell will have two threshold voltages, corresponding to each of its programmed and erased states. The floating gate voltage required to invert the transistor (V
th
) does not change for a given cell, but the control gate voltage to invert the transistor (that is, to bring the floating gate to V
th
) differs depending upon the charged or discharged state of the cell.
Prior to shipping a non-volatile memory cell product, a manufacturer will generally test the cells to guarantee that each bit has a good margin, and that the bit will maintain its programmed or erased state over the lifetime of the cell. The “margin” is the voltage required on a cell's control gate to cause a change in the state of a bit of memory. As illustrated in
FIG. 2
, since a programmable cell has two threshold voltages, it will have two margin voltages: One for the programmed state and one for the erased state. In an EEPROM cell, an erased bit will have a lower margin voltage, typically between about −5V to 0V, and a programmed bit will typically have a higher margin voltage, typically between about 3V and 8V.
In normal cell operation, the EEPROM's control gate will typically be set at a value between the programmed and erased ranges, for example 1.7V. For margin testing, however, the control gate voltage is swept through ranges of voltages to determine the cell's threshold voltages. For example, for a charged cell the control gate may typically be swept from about 3V to 8V; and from about −5V to 0V for an erased cell.
In practice, margin testing requires a detector to determine when a margin voltage has been reached. This role is typically performed by a sense amplifier, such as that described with reference to
FIG. 1A. A
particular margin voltage will correspond to a “trip current” (I
trip
), which is that curren
Costello John C.
Madurawe Raminda U.
Mielke Bruce F.
Sansbury James D.
Wong Myron W.
Beyer Weaver & Thomas LLP
Ho Hoai
Pham Ly Duy
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