Electrical computers and digital processing systems: memory – Address formation – Hashing
Patent
1994-04-04
1998-10-27
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Address formation
Hashing
711113, 711220, 711217, 711213, G06F 926
Patent
active
058290516
ABSTRACT:
An apparatus for allocating data to and retrieving data from a cache includes a memory subsystem coupled between a processor and a memory to provide quick access of memory data to the processor. The memory subsystem includes a cache memory. The address provided to the memory subsystem is divided into a cache index and a tag, and the cache index is hashed to provide a plurality of alternative addresses for accessing the cache. During a cache read, each of the alternative addresses are selected to search for the data responsive to an indicator of the validity of the data at the locations. The selection of the alternative address may be done through a mask having a number of bits corresponding to the number of alternative addresses. Each bit indicates whether the alternative address at that location should be used during the access of the cache in search of the data. Alternatively, a memory device which has more entries than the cache has blocks may be used to store the select value of the best alternative address to use to locate the data. Data is allocated to each alternative address based upon a modified least recently used technique wherein a quantum number and modula counter are used to time stamp the data.
REFERENCES:
patent: 5418921 (1995-05-01), Cortney et al.
patent: 5509135 (1996-04-01), Steely, Jr.
patent: 5544345 (1996-08-01), Carpenter et al.
Applicant's admitted prior art in the disclosure, Apr. 1994.
Anant Agarwal, "Analysis of Cache Performance for Operating Systems and Multiprogramming" Kluwer Academic Publishers, pp. 003-006.
Fossum Tryggve
Gillett Jr. Richard B.
Steely, Jr. Simon C.
Chan Eddie P.
Digital Equipment Corporation
Nguyen T. V.
Pappas Joanne N.
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