Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2007-10-30
2007-10-30
Shah, Sanjiv (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S103000, C711S118000, C711S128000, C711S133000, C711S134000, C711S136000, C711S144000, C711S145000, C711S152000, C711S165000, C713S001000, C713S002000, C713S100000, C712S208000, C712S209000, C712S211000, C712S213000
Reexamination Certificate
active
10146537
ABSTRACT:
A ROM patching apparatus for use in a data processing system that executes instruction code stored in the ROM. The ROM patching apparatus comprises: 1) a patch buffer for storing a first replacement cache line containing a first new instruction suitable for replacing at least a portion of the code in the ROM; 2) a lockable cache; 3) core processor logic operable to read from an associated memory a patch table containing a first table entry, the first table entry containing 1) the first new instruction and 2) a first patch address identifying a first patched ROM address of the at least a portion of the code in the ROM. The core processor logic loads the first new instruction from the patch table into the patch buffer, stores the first replacement cache line from the patch buffer into the lockable cache, and locks the first replacement cache line into the lockable cache.
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Parthasarathy Sivagnanam
Risso Alessandro
Jorgenson Lisa K.
Li Zhuo H.
Munck William A.
Shah Sanjiv
STMicroelectronics Inc.
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