Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-06
2001-04-17
Crane, Sara (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S599000, C438S622000
Reexamination Certificate
active
06218225
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor integrated circuit devices, and more particularly, to the integrated circuit devices having a multiplicity of components generally referred to as gate arrays.
2. Description of the Prior Art
Gate array devices are fabricated to include a multiplicity of component sets. Each component set, typically referred to as a base cell, has a plurality of components which can be configured to implement a wide variety of circuit sets in response to the requirements of the specific application. As a practical matter, the circuit most widely implemented by gate arrays are D-type multivibrator (flip-flop) circuits. In general, 60% of the circuits implemented by gate arrays can be flip-flop circuits.
U.S. Pat. No. 5,591,995, issued on Jan. 7, 1997 in the name of the inventor of the present Application and assigned to the same assignee as the present Application, discloses a base cell configuration that can be used, inter alia, to implement the D-type flip-flop circuit. A slightly modified version of the prior art base cell configuration of U.S. Pat. No. '995 is shown in a plan view in FIG.
1
A. In
FIG. 2A
, a schematic circuit diagram of the components implemented by this prior art base cell is shown. In
FIG. 3A
, a circuit diagram of a D-type flip-flop circuit to be implemented by the base cell is shown. In
FIG.4A
, a plan view of the metal layer required to provide a D-type flip-flop circuit in the base cell shown in
FIG. 1A
is illustrated.
Referring once again to FIG.
1
A and
FIG. 2A
, the plan view representation of the prior art base cell and the circuit component schematic representation of the prior art base cell, respectively, are shown. The base cell includes CL and CS sites. Generally, the CL sites have transistors with larger CMOS gate widths, while the CS sites generally have transistors with smaller CMOS gate widths. Each CL site includes a pair of n-channel pass transistors
6
, a pair of n-channel transistors
8
, a pair of p-channel transistors
10
and a pair of small p-channel transistors
12
. The pass transistors
6
are typically used as pass gates in conjunction with a static random access memory (SRAM). However, the pass transistors can be used of other logic gates in configuring the gate array. Transistors
8
and
10
are typically used in combination to form a CMOS logic gate or drive circuitry. With respect each CS site, this site includes a pair of pass transistors
6
, two pairs of n-channel transistors
14
and two pairs of p-channel transistors
16
. Transistors
14
and
16
are matched as closely as possible to one half the size of transistors
8
and
10
.
Referring to
FIG. 3A
, a schematic circuit diagram of a D-type flip-flop circuit that can formed from the base cell illustrated in
FIGS. 1A and 2A
is shown. The input data signal node D is coupled to an input terminal of inverting amplifier
31
, while the input clock signal node CLK is coupled to the input terminal inverting amplifier
32
. The output terminal of inverting amplifier
31
is coupled to the DN node, the DN node also being coupled to a data input terminal of pass-gate
33
. The output terminal of inverting amplifier
32
is coupled to node CLKZ, the node CLKZ also being coupled to an input terminal of inverting amplifier
34
, to a control terminal of pass-gate
33
, to a control terminal of pass-gate
35
, and to a control terminal of pass-gate
38
, and to a control terminal of pass-gate
39
. The output terminal of pass-gate
33
is coupled to node N
1
, node N
1
also being coupled to an input terminal of inverting amplifier
36
and to an output terminal of pass-gate
35
. The output terminal of inverting amplifier
34
is coupled to node CLKT, the node CLKT also being coupled
33
to a control terminal of pass-gate
33
, to a control terminal of pass-gate
35
, to a control terminal of pass-gate
38
and to a control terminal of pass-gate
39
. An output terminal of inverting amplifier
36
is coupled to node N
5
, node N
5
also being coupled to an input terminal of inverting amplifier
37
and to an input terminal of pass-gate
38
. An output terminal of inverting amplifier
37
is coupled to node N
3
, node N
3
also being coupled to an input terminal of inverting amplifier
35
. The output terminal of pass-gate
38
is coupled to node N
2
, node N
2
also being coupled to input terminal of inverting amplifier
40
and to an output terminal of pass-gate
39
. The output terminal of inverting amplifier
40
is coupled to node N
6
, node N
6
also being coupled to an input terminal of inverting amplifier
42
and to an input terminal of inverting amplifier
41
. An output terminal of inverting amplifier
41
is coupled to node N
4
, node N
4
also being coupled to an input terminal of pass-gate
39
. The output terminal of inverting amplifier
42
is the output signal node Q.
Referring to
FIG. 4A
, the metal layer required to implement a D-type flip-flop circuit for the prior art base cell of FIG.
1
A and
FIG. 2A
is shown. Each of the nodes, N
1
-N
6
, shown in
FIG. 3A
are identified. Note that the implementation of D-type flip-flop circuit requires components from each of the four sites comprising a base cell. Several of the nodes are implemented by a plurality of conducting paths. These nodes are coupled through conducting paths, formed below the metal layer, the conducting paths and the metal layer traces being coupled by conducting plugs. Using the design rules, e.g., for the distance between specified areas, the width of preselected paths, etc., the pitch of the cell, i.e., the spacing between uniformly spaced grid markers is 2.4 um in both the x-direction and in the y-direction. The each site of the base cell is four grid lengths in the x-direction and 17 grid lengths in the y-direction.
Because of the frequency of the implementation of D-type flip-flop circuits, a need has been felt to provide a base cell in which the D-type flip-flop circuit can be implemented without requiring components from all of the sites of the base cell. A need has further been felt to provide a technique for reducing the pitch of a base cell while still maintaining the same design rules resulting in the prior art base cell. Finally, it would be desirable to arrange the components of the base cell to provide a simplified interconnect metal layer coupling the components.
SUMMARY OF THE INVENTION
The aforementioned and other features are accomplished, according to the present invention, by providing a gate array having large and small sites, each site having a plurality of transistors arranged in pairs. Each pair of transistors is fabricated having a common source drain region, i.e., having a common moat region. At least one of the moat regions has been relocated to form more easily a complementary gate.. In addition, at least one large moat region is fabricated with an extended missing section to permit a conducting plug to pass thereby, while maintaining a base cell having a reduced pitch. In this manner, not only can size of the base cell be reduced, but the coupling of base cell components into a D-type flip-flop circuit can be accomplished using three base cell sites rather than the four base cell sites of the prior art.
These and other features of the present invention will be understood upon the reading of the following description in conjunction with the Figures.
REFERENCES:
patent: 5428255 (1995-06-01), Wall
patent: 5591995 (1997-01-01), Shaw
Brady III Wade James
Crane Sara
Stewart Alan K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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