Apparatus and method for encoding a low density parity check...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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C714S800000, C714S801000

Reexamination Certificate

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10834069

ABSTRACT:
An apparatus and method for generating an encoding matrix for a low density parity check (LDPC) code having a dual-diagonal matrix as a parity check matrix are disclosed. The apparatus and method construct an information sub-matrix of the encoding matrix with a predetermined number of square matrixes according to a predetermined code rate such that each of the square matrixes has columns and rows with a weight of 1 and has a different offset value, combine the square matrixes with the dual-diagonal matrix, and perform inter-row permutation on the information sub-matrix.

REFERENCES:
patent: 7089479 (2006-08-01), Matsumoto
patent: 2004/0034828 (2004-02-01), Hocevar
patent: 2004/0255217 (2004-12-01), Garrett et al.

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