Apparatus and method for enabling a multi-processor...

Details Apparatus and method for enabling a multi-processor... Apparatus and method for enabling a multi-processor...

2008-04-15

2008-04-15

Le, Don (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S082000

Reexamination Certificate

active

07358758

ABSTRACT:
The present invention provides a technique for enabling multiple devices to be interfaced together over a bus that requires dynamic impedance controls. In one embodiment, an apparatus is provided for enabling a multi-device environment on a bus, where the bus requires active termination impedance control. The apparatus includes a first node and multi-processor logic. The first node receives an indication that a corresponding device is at a physical end of the bus or that the corresponding device is an internal device. The multi-processor logic is coupled to the first node. The multi-processor logic controls how a second node is driven according to the indication, where the second node is coupled to the bus.

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