Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-02-23
2001-07-10
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000, C714S735000
Reexamination Certificate
active
06260167
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to testing of data communication networking devices, more particularly to a transceiver employed in an Ethernet type network.
2. Background Art
Device testing plays a critical role in the manufacturing of networking equipment. Manufacturers are continually seeking ways to produce these equipment economically. One effective way is to reduce testing costs. Because of the prevalence of local area networks, even a small cost reduction measure translates into a competitive edge in the marketplace.
Local area networks use a network cable or other network media to link nodes (e.g., workstations, routers and switches) to the network. Each local area network architecture uses a media access control (MAC) enabling network interface device at each network node to share access to the media. Physical (PHY) layer devices are configured for translating digital packet data received from a MAC across a standardized interface, e.g., a Media Independent Interface (MII), into an analog signal for transmission on the network medium, and reception of analog signals transmitted from a remote node via the network medium. An example is the 100Base-TX Ethernet (IEEE Standard 802.3u) transceiver, which is configured for transmitting and receiving a Multi-level Transmission-3 (MLT-3) encoded analog signal over unshielded (or shielded) twisted pair copper wiring.
To transmit a MLT-3 encoded signal across the media, 4-bit codes from the MII are supplied to a 4B/5B (4 bit/5 bit) encoder. The newly generated 5-bit symbols are serialized and outputted onto the physical media as MLT-3 encoded signals at 125 Mbps. The physical channel rate of 125 Mbps results from use of a 25 MHz internal clock that is multiplied by 5. The physical channel rate of 125 Mbps, at the receive end, is effectively reduced to a 100 Mbps physical layer interface because the received 5-bit symbols are decoded back into 4-bit MII codes (i.e., nibbles). Although the physical channel rate is 125 MHz, the MII utilizes a 25 MHz clock. A digital phase-locked loop (PLL) recovers the clock information. A deserializer performs a serial to parallel conversion in which one serial bit translates to 5 outgoing parallel bits to maintain the 125 MHz rate.
On the receive side of the transceiver, there is a concern with phase alignment during testing. At power up or reset, the PLL requires a period of time to calibrate itself, and therefore, can not immediately align itself with the incoming signals. The number of 125 MHz clock cycles that are generated by the receive side is not deterministic until the PLL stabilizes. As a result, alignment is unknown until stabilization of the PLL. Factors that contribute to the non-deterministic nature of the clock cycles include the unknown initial state of the PLL, process variation, and temperature and voltage at the time of power-up. Under normal operation, the non-deterministic nature of the number of clock cycles is a “don't care” during power up. However, this poses a problem during testing of the PHY devices. In particular, the 125 MHz clock is divided by 5 to generate a 25 MHz clock. Since the number of 125 MHz receive clock cycles is not exactly known, the divided by 5 clock and parallel data can be phase shifted in any one of 5 possible positions (i.e., PHY pop-up positions), shown in FIG.
1
. Hence, the PHY receiver must determine PHY pop-up position and extract clock information from the incoming MLT -3 signals so that data can be properly retrieved. PHY pop-up position refers to the bit sequence that is conveyed by the received signal during power up or reset of the PHY device.
FIG. 1
is a signal diagram illustrating the relationship between the received serialized data stream and the converted parallel data. The received bit stream
10
are designated as a serialized sequence of bits A, B, C, D, E, F, G, H, and I. These designations are merely to convey relative bit positions, which are unknown. As previously mentioned, five possible PHY pop-up positions
12
,
14
,
16
,
18
, and
20
exist from the serialized data stream
10
. At power up, the PHY receiver may receive bits beginning with anyone of these positions. For example, the first PHY pop-up position
12
may start with bit A, in which case the retrieved bit sequence
22
is ABCDE. If the 25 MHz clock starts when bit B is received (
14
), the bit sequence yields BCDEF
24
. With a PHY pop-up position of C (
16
), the sequence
26
is CDEFG. Sequence DEFGH (
28
) stems from the 25 MHz clock starting at bit D (
18
). If the PHY pop-up position is at E (
20
), the sequence is EFGHI (
30
).
In an operational network, the PHY device achieves alignment by seeking out the JK delimiter symbols using back-end logic. Back-end logic refers to processing capabilities of other components or higher level processes. In a test environment, however, certain context-specific information (e.g., alignment, clock, etc.) are not present. Specifically, alignment is problematic because back-end logic is not available in the test environment to extract the needed information. Rather, testers compare the output of the device against a known set of signal/bit patterns on a cycle by cycle basis. This poses a problem because the tester does not know to which of the five possible test patterns to use for proper comparison. Testing on a cycle by cycle basis, traditionally, has required performing multiple iterations of a test procedure (i.e., multiple passes) to calculate PHY pop-up position and clocking information. These two parameters are used to determine whether the PHY device is operating correctly. The conventional test procedure involves iterative steps to attempt to lock on the edges of the incoming signals. This approach also examines the actual individual signals off the MII to determine whether they are valid, thereby expending a large amount of time. In addition, such testing may require development of new circuitry to rapidly determine the clock signal and the PHY pop-up position. Both factors of increased testing time and development of new circuitry contribute to a significant increase in production costs.
SUMMARY OF THE INVENTION
There is a need for an arrangement for testing a PHY receiver device in a single test without the necessity for back-end logic. There is a need to test a PHY device without having to align the output signals of the PHY device. Further, there is a need to conduct PHY device testing by using existing error checking logic.
These and other needs are attained by the present invention, where a system for testing a networking device comprises a pattern generator for generating a known valid bit pattern for a data packet. A physical layer (PHY) device is configured for outputting a data signal and a receive clock signal in response to the known valid bit pattern and based on a prescribed operation of the PHY device. The PHY device comprises an error checking circuit configured for detecting an error in a received data frame. The error checking circuit selectively outputs a pass signal indicating operation of the PHY device in accordance with the prescribed operation based on the data signal. Because only the pass signal needs to be examined for testing purposes, there is a significant reduction of testing time during the production of the networking devices.
According to one aspect of the present invention, a system for testing a networking device comprises a pattern generating circuit for generating a known bit pattern for a data packet in accordance to a prescribed network protocol. A PHY device is configured for outputting a data signal and a receive clock signal in response to the known valid bit pattern and based on a prescribed operation of the PHY device. An error checking circuit is configured for detecting an error in a received data frame, the error checking circuit selectively outputting a pass signal indicating operation of the PHY device in accordance with the prescribed operation based on the data signal. Hence, under this approach, the produ
Huang Yuhua
Lo William
Advanced Micro Devices , Inc.
De'cady Albert
Torres Joseph D.
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