Apparatus and method for determining on die termination...

Details Apparatus and method for determining on die termination... Apparatus and method for determining on die termination...

2007-08-07

2008-10-14

Cho, James H (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S016000

Reexamination Certificate

active

07436204

ABSTRACT:
For determining an on die termination (ODT) mode in a semiconductor memory device, a first mode determining unit determines whether or not a normal ODT mode is enabled from performing a logic operation on a first set of signals. A second mode determining unit determines whether or not a dynamic ODT mode test is enabled from performing a logic operation on a second set of signals. One of the normal and dynamic ODT modes is enabled with more flexibility.

REFERENCES:
patent: 6847225 (2005-01-01), Viehmann et al.
patent: 7196966 (2007-03-01), Jin
patent: 7285979 (2007-10-01), Janzen et al.
patent: 7317328 (2008-01-01), Kim
Korean Patent Application No. 1020040020764 to So et al., having Publication date of Sep. 29, 2005 (w/ English Abstract page).
Korean Patent Application No. 1020040066531 to Park, having Publication date of Jun. 29, 2005 (w/ English Abstract page).
Japanese Patent Application No. 2000-090387 to Hirobumi, having Publication date of Oct. 12, 2001 (w/ English Abstract page).

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