Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1998-10-19
2001-07-03
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S200000
Reexamination Certificate
active
06256755
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the detection of imminent failures of an array of NVRAM cells. Specifically, a circuit is described which will monitor the degradation of an array of NVRAM cells so that a timely replacement of the array may be made.
NVRAM arrays are commonly found in devices such as portable calculators, smart cards and medical record storage devices. In the smart card application they are typically used as a permanent memory to store specific transaction data which is necessary for using the smart card. Each cell of the NVRAM may be of the type which comprises a stacked gate cell formed from a floating gate structure located under a control gate, with a source and drain diffusion region on either side of the gate structures. Each stacked gate cell of the array is programmed by storing a charge representing a digital binary
1
value in the a floating gate of the cell. The NVRAM cells are erased by applying a common erasing potential to the sources of all the cell transistors in the NVRAM array.
NVRAM arrays, however, have a limited life. Each successive erasure of an NVRAM cell tends to degrade the cell so that erasure becomes more difficult with time. NVRAM cells fail catastrophically as they degrade, and if the failure is not accurately predicted, valuable data may be lost from the NVRAM array. The time it takes to erase a programmed cell by removing the charge from the floating gate is an endurance factor which represents the useful life of the array. one known technique for avoiding the catastrophic failure of NVRAM cells, the number of times that the array of NVRAM cells has been erased is used as a predictor of catastrophic failure. When the total erasure count reaches a predetermined experimentally derived value, it is deemed time to replace the NVRAM array in order to avoid a catastrophic failure.
The foregoing technique is disadvantageous in that it can result in the replacement of an array of NVRAM cells prematurely when a significant amount of life remains in the NVRAM cells.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a method to test NVRAM cells for a potential defect.
It is a more specific object of this invention to monitor the degradation of NVRAM cells over time to identify a potential catastrophic failure.
These and other objects of the invention are accomplished in a method and apparatus which continually measures the degradation of individual cells of an NVRAM array. The degradation of the NVRAM array is determined by monitoring the change in erasure characteristics over time. As the erasure characteristics of each cell reach a particular threshold, a flag is set warning the user that continued use may result in a catastrophic failure of the NVRAM array.
In a first embodiment of the invention, two characteristics representing the degradation of the NVRAM array are monitored. The first is the erasure time which increases during normal use of the NVRAM array. The erasure time is compared with a threshold and used to indicate an imminent failure. The change in erasure time as a function of number of erasures, representing an erasure acceleration, is used as the second characteristic to detect a potential failure in the NVRAM cell array. When either characteristic exceeds a respective threshold, the potential failure of the NVRAM cell array is regarded as imminent.
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Hook Terence B.
Lam Chung H.
Lee Eric S.
Nakos James S.
Rovedo Nivo
Chung Phung M.
Connolly Bove Lodge & Hutz
International Business Machines - Corporation
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