Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2005-05-20
2009-12-08
Chaudry, M. Mujtaba K (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S758000, C713S186000
Reexamination Certificate
active
07631241
ABSTRACT:
An apparatus and method for decoding low density parity check (LDPC) codes are provided. A memory module configured by a plurality of unit memories stores a reliability value. Variable node processors perform a computation associated with a variable node, and update data of the memory module in a column direction, respectively. Check node processors perform a computation associated with a check node, and update data of the memory module in a row direction, respectively. A parity checker determines if all errors have been corrected such that an iterative decoding process is performed. A memory access control module selects a unit memory to be updated by a variable node processor or a check node processor.
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Kim Han-Ju
Kim Min-Goo
Park Sung-Jin
Yu Nam Yul
Ahmed Enam
Chaudry M. Mujtaba K
Roylance Abrams Berdo & Goodman L.L.P.
Samsung Electronics Co,. Ltd.
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