Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
1998-12-29
2001-12-25
DeCady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
Reexamination Certificate
active
06334204
ABSTRACT:
CLAIM OF PRIORITY
This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. §119 from an application for METHOD FOR CORRECTING ONE BIT ERROR OF PARALLEL DIGITAL BUS AND APPARATUS THEREOF earlier filed in the Korean Industrial Property Office on the Dec. 30, 1997 and there duly assigned Ser. No. 79016/1997.
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention is related to a parallel digital bus for transmitting data in a digital system. More specifically, the present invention relates to an apparatus and method for correcting a one-bit error occurring in the parallel digital bus so as to maintain the performance of the system.
2. Related Art
Contemporary apparatuses and methods for correcting errors occurring in data transmitted over a parallel digital bus are burdened by serious drawbacks. Specifically, when a one-bit error occurs in such data, the error cannot and is not effectively corrected under certain circumstances.
For example, as explained in more detail below, if an error bit is found, the arrangement checks for the existence of the error by utilizing the parity bit. If the bit error is temporary, the transmitter retries transmitting the data in a software method so as to maintain the performance, but the error cannot be corrected. Therefore, if a one-bit error occurred, the system cannot maintain normal operation.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a circuit and method for correcting a one-bit error when a bit in the hardware of the system is fixed as 0 or 1 to generate an error in the parallel digital bus including a parity bit.
To achieve an object of the present invention, a preferred embodiment of an apparatus for correcting a one-bit error of a parallel digital bus includes: a transmitter; a first data corrector block for receiving the data from the transmitter so as to store the received data; a second data corrector block for receiving a signal from the transmitter so as to check for the existence of the parity error of the data received from the first data correction block and, if a parity error is found, modifying the received data; and a receiver for selectively receiving the data from the first data corrector block or the second data corrector block according to the existence of the parity error.
To achieve another object of the present invention, a preferred embodiment of a method for modifying a one-bit error in the parallel digital bus comprises the steps of: storing the data to a first data storage in a first data corrector, transmitting the data to a second data corrector; checking for a parity error in the transmitted data; storing the transmitted data to the second data storage; storing the transmitted data to the origins data storage; transmitting the data of the first data corrector to the receiver; if no parity error is found after checking the parity, shifting one bit of the data of the first data storage and tans the shifted data to the selector; if a parity error is found after checking the parity, shifting one bit of the data of the second data storage; if a parity error is found after checking the parity, modifying the error by utilizing the data stored in the first data storage, the data stored in the second data storage, and the data stored in the original data storage; selecting the data stored in the first data storage in the case of no error, or the modified data in the case of the existence of one error; and transmitting the selected data to the receiver.
Exemplars of recent efforts in the art include U.S. Pat. No. 4298982 for Fault-Tolerant Interface Circuit For Parallel Digital Bus issued to Auerbach. The aforementioned patent is different from the present invention in that the invention avoids the disadvantages of a complicated bus circuit and increasing bus error probability.
REFERENCES:
patent: 3659089 (1972-04-01), Payne et al.
patent: 3699323 (1972-10-01), Reinheimer
patent: 4298982 (1981-11-01), Auerbach
patent: 4348742 (1982-09-01), O'Brian
patent: 4417339 (1983-11-01), Cantarella
patent: 4429391 (1984-01-01), Lee
patent: 4556978 (1985-12-01), Kregness et al.
patent: 5392299 (1995-02-01), Rhines et al.
“Error Control Systems”, Stephen B. Wicker, Prentice Hall, 1995.*
M. Morris Mano, “Digital Logic and Computer Design”, Prentice Hall, 1979.
Bushnell , Esq. Robert E.
De'cady Albert
Samsung Electronics Co,. Ltd.
Torres Joseph D.
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