Apparatus and method for controlling frequency of an I/O...

Details Apparatus and method for controlling frequency of an I/O... Apparatus and method for controlling frequency of an I/O...

2006-04-24

2008-10-28

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S726000, C714S030000, C714S034000, C714S707000, C714S701000, C714S724000, C714S744000, C702S089000, C702S106000, C702S125000

Reexamination Certificate

active

07444570

ABSTRACT:
A test system including a device under test (DUT) and a tester, where the DUT includes I/O interface logic and a clock circuit. The clock circuit includes a core clock circuit, a pad clock circuit, a test clock circuit, and a select circuit. The core clock circuit generates a core clock signal enabling full speed operation of core circuitry of the IC during test mode. The pad clock circuit generates a preliminary clock signal suitable for normal operation, and the test clock circuit generates a test clock signal suitable for operating the I/O interface logic during the test mode. The select circuit selects, based on the test signal, between the test clock signal and the preliminary clock signal as the pad clock signal. The tester provides the bus clock signal and indicates the test mode to the DUT via the I/O interface logic.

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