Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent
1997-04-22
1999-11-16
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
G06F 1110
Patent
active
059876387
ABSTRACT:
A Viterbi calculator performs additions in parallel with comparison to compute the result of a single Viterbi equation in a single clock cycle. Therefore, the results of a butterfly operation involving two Viterbi equations can be computed in a single clock cycle by use of two Viterbi calculators. Alternatively, the butterfly operation can be implemented by a single Viterbi calculator used in a pipelined manner, although the throughput is at the rate of every two clock cycles. When a single Viterbi calculator is used in the pipelined manner, two multiplexers are used to alternately swap the constant values being supplied to the Viterbi calculator. The pipelined use of a single Viterbi calculator requires less space on an integrated circuit die than the parallel use of two Viterbi calculators, and is useful in applications where the variable data is available every two clock cycles (e.g. due to latency in accessing memory).
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Padmanabhan Satish
Yu Robert K.
Cady Albert De
Chase Shelly A
LSI Logic Corporation
Suryadevara Omkar
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