Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2006-07-18
2010-02-23
Torres, Juan A (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S376000
Reexamination Certificate
active
07668277
ABSTRACT:
For clock and data recovery (CDR), a clock processor generates sampling clock signals from original phase-shifted clock signals each having a frequency that ⅛ of a frequency of an input data signal. The sampling clock signals are used to sample the input data signal for generating error signals and reference signals that determine a voltage control signal that indicates a clock frequency of the original clock signals generated by a voltage controlled oscillator (VCO).
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Choi Monica H.
Samsung Electronics Co,. Ltd.
Torres Juan A
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