Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Timing
Reexamination Certificate
2001-03-19
2004-09-21
Frejd, Russell (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Timing
C703S002000, C703S014000
Reexamination Certificate
active
06795802
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a technique for predicting aging property deterioration of a large scale semiconductor integrated circuit (hereinafter, abbreviated as LSI) caused by the hot carrier phenomenon (deterioration) or the like, and obtaining a suitable aging deterioration margin amount as an allowance to be made at time of designing LSIs or inspecting LSIs.
In recent years, LSIs have reached the point where several ten million or more MOS transistors are integrated to realize various functions on one chip. In such LSIs, it is necessary that a tolerance, that is, a margin amount is included for various properties in the design stage so that the LSIs can operate normally, even if the supply voltage or the temperature used are varied, or the properties are not uniform. In the following description, delay of signals is used as an example of the margin amount.
In general, a LSI can be disintegrated into a plurality of basic units, each of which includes a certain number of stages of circuits
22
(N stages in
FIG. 1
) between, for example, flip-flops
21
,
21
, that is, a plurality of signal paths
20
, as shown in FIG.
1
. Each of the circuits
22
includes logic circuits and wiring connecting these logic circuits in many cases. The delay of a signal when the signal propagates through a series of circuits
22
of the signal path
20
is required to be within a predetermined period of time, that is, a cycle time (the inverted number of the operation frequency or the clock frequency in many cases) of a clock signal
23
supplied to the flip-flops
21
,
21
, as shown in the following equation (1).
t
cycle≧&Sgr;
ti+K
(i=1 to N) (1)
where t cycle is a cycle time, which is a design target property, &Sgr;ti is the total of signal propagation delay between input and output terminals of each circuit i (
22
) between the flip-flops
21
, that is, a signal path delay in the LSI, and K is the sum of the setup time of the flip-flops
21
and the skew of the clock signal
23
.
The maximum value (the worst value) of the &Sgr;ti can be obtained by simulation of delay variation in a circuit operation, or a method of using derating factors, which are coefficients that represent the influence of various delay variation factors, is known as an approach for saving work load for design. More specifically, this is a method of designing by roughly estimating the worst conditions from a typical delay, as shown in the following equation (2).
t
worst=
t
typ
×P×V×T
(2)
where t worst is the maximum value (the worst value) of each signal path delay, t typ is a typical value of each signal path delay, P is a delay variation coefficient in accordance with production deviation, V is a delay variation coefficient in accordance with the amount of a supply voltage variation width, and T is a delay variation coefficient in accordance with the amount of a temperature variation width. The difference between the t worst and the t typ is a margin amount for the delay variation to be considered.
The typical value t typ of the signal path delay can be obtained by a quite smaller scale simulation than by a simulation where the maximum value of the delay variation is obtained. If the typical values of all the signal path delays of the LSI are obtained, the worst value can be obtained efficiently, simply by multiplying these typical values by the derating factors P, V, and T. Such an approach is more often used for LSI design for specific applications such as ASIC than for the types for which a custom design is often used, such as microprocessors.
LSIs have their lifetime as other products, and disorder or malfunction occurs in a certain period of operation time after production. As the main causes of disorder or malfunction, property deterioration due to the hot carrier phenomenon, or breakage of wiring or short-circuit due to electromigration is known. In particular, in recent LSIs, miniaturization of transistors has been rapidly developed with the development of production techniques, so that the electric field in each component of the LSI tends to be high. Therefore, a high electric field occurring in the vicinity of a drain of MOS transistor causes impact ionization of carriers, so that hot carriers having high energy are likely to be generated. The hot carriers cause damage to a gate oxide film, and thus causes aging changes in the threshold voltage or the drain current of a transistor over time, that is, property deterioration. Consequently, this may change the operation frequency property or the like of the LSI, which is an assembly of the transistors, and finally may cause malfunction to the LSI. Therefore, in the design of the LSIs, it is essential to ensure the reliability in accordance with a desired lifetime of the product, so that in general, a design tolerance for deterioration of the LSI, that is, an aging deterioration margin amount is included.
More specifically, the signal path delay shown in the equation (1) is not constant throughout the elapse of the operation time of the LSI, but is changed by the hot carrier phenomenon or the like. The degree of the delay change due to the hot carrier phenomenon depends on the type of the circuit, the operating conditions of the circuit (e.g., the supply voltage, the temperature, the number of switching operations, the slew rate of an input signal, whether a signal transition is to go high or low, and an output signal load or the like), and the production deviation of the circuit properties, and usually is increased. Taking this aging deterioration into account, it is not sufficient to satisfy the equation (1) and it is necessary to satisfy the following equation (3) in order to guarantee the operation throughout the product lifetime of the LSI.
t
cycle≧&Sgr;(
ti+&Dgr;ti
)+
K
(
i=
1 to
N
) (3)
where &Sgr; &Dgr;ti is a variation amount of the signal path delay due to deterioration. Thus, when designing a LSI, it is necessary to make allowance for the influence of delay increments due to deterioration, and to include a design tolerance, that is, an aging deterioration margin amount so that the equation (3) is satisfied.
If the aging deterioration margin amount included at the time of the design of the LSI is too small, the reliability is not sufficient so that a malfunction may be caused before the desired product lifetime expires in the future. On the other hand, if the aging deterioration margin amount is too large, the reliability is excessive. In general, the reliability and the performance of the LSI has a trade-off relationship, so that excessive reliability results in degraded performance (e.g., operation frequency) of the LSI. Therefore, when a suitable aging deterioration margin amount cannot be set, it is difficult to develop LSIs for which both high performance and reliability are required, such as microprocessors.
Examples of a method of testing the design of a LSI with making an allowance for aging deterioration as described above include a method described in U.S. Pat. No. 5,634,001. In this method, a LSI is designed by using the simulation technique disclosed in U.S. Pat. No. 5,533,197 to predict the operation timing property of the LSI after the operation for the desired product lifetime, that is, all the signal path delays after deterioration of the LSI shown in equation (3), based on the design information of the LSI in the design process, and confirming with simulations that the delay after deterioration of the most delayed signal path (critical path) is within the cycle time. In this manner, it is attempted to include neither too much nor too little aging deterioration margin amount.
However, the method for predicting all the signal path delays after deterioration of the LSI with the simulation technique as described above results in a large amount of calculations, so that calculation takes much time, and a large scale apparatus is required.
On the other hand, similarly to the margin amount before deteriorat
Iwanishi Nobufusa
Kawakami Yoshiyuki
Yonezawa Hirokazu
Frejd Russell
Matsushita Electric - Industrial Co., Ltd.
McDermott Will & Emery LLP
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