Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Testing or evaluating
Reexamination Certificate
2006-11-28
2011-12-20
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Testing or evaluating
C716S052000, C716S112000, C702S059000, C702S117000
Reexamination Certificate
active
08082534
ABSTRACT:
A fault coverage calculating apparatus includes: an extraction module configured to extract information on a pair of wiring lines including a length of the pair adjacent within a predetermined distance range and a distance between the pair and bridge fault information corresponding to the pair from layout information of a semiconductor integrated circuit; a test module configured to perform a determination test for determining whether a bridge fault occurring in the pair is detected by using a bridge fault test pattern of a target; and a calculation module configured to calculate a bridge fault coverage to which the length and the distance are weighted, based on the information on the pair of wiring lines, the bridge fault information, a result of the determination test, and a bridge fault incidence depending on the distance.
REFERENCES:
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patent: 2006/0005094 (2006-01-01), Nozuyama
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Y. Nozuyama et al., “A Method for Estimating and Enhancing Test Quality Using Layout Information”, Technical Report of IEICE, vol. CPM2002-152, Jan. 2003, pp. 1-6.
C.E. Stroud et al., “Bridging Fault Extraction from Physical Design Data for Manufacturing Test Development,” Proc. IEEE International Test Conference, Oct. 2000, pp. 760-769.
S. Sengupta et al., “Defect-Based Test: A Key Enabler for successful Migration to Structural Test,” Intel Technology Journal, 1999, pp. 1-14.
Foley & Lardner LLP
Kabushiki Kaisha Toshiba
Siek Vuthe
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