Apparatus and method for an address generation circuit

Details Apparatus and method for an address generation circuit Apparatus and method for an address generation circuit

2008-05-27

2008-05-27

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Combining two or more values to create address

C711S217000, C708S490000

Reexamination Certificate

active

10956164

ABSTRACT:
A method and apparatus for an address generation circuit. In one embodiment, the method includes computing a carry-in for at least one group of a predetermined number of bits of a propagate and a generate signal formed from a plurality of logical address components. Once the carry-in is computed, a plurality of conditional sums are generated for a logic0carry-in and a logic1carry-in. Subsequently, a sum is selected from the plurality of conditional sums to form a first portion of an effective address from the logical address components in a first stage and a second portion of the effective address in a second stage. In one embodiment, a fully dynamic high-performance sparse tree adder circuit that generates one in four carries, is used to form an address generation circuit, in accordance with one embodiment. Other embodiments are described and claimed.

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patent: 2004/0078767 (2004-04-01), Burks et al.

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