Apparatus and method for addressing a cache memory in a computer

Details Apparatus and method for addressing a cache memory in a computer Apparatus and method for addressing a cache memory in a computer

1997-02-14

1999-01-12

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711 4, 711200, 395381, 395383, 365 49, 36518901, 36518902, 36518905, 36523003, G06F 1200

Patent

active

058600922

ABSTRACT:
A tag memory circuit includes an address index input, an address offset input and an integrated adder and pre-decode circuit. The integrated adder and pre-decode circuit has a first addend input coupled to the address index input, a second addend input coupled to the address offset input, and a pre-decoded sum output. A final row decode and word line driver circuit is coupled to the pre-decoded sum output and generates a word line output which is coupled to the address inputs of a tag memory array. The data outputs of the tag memory array are coupled to a sense amplifier.

REFERENCES:
patent: 5337415 (1994-08-01), Delano et al.
patent: 5475825 (1995-12-01), Yonezawa et al.
patent: 5577223 (1996-11-01), Tanoi et al.
patent: 5687339 (1997-11-01), Hwang
patent: 5689672 (1997-11-01), Witt et al.

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