Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2003-06-05
2004-11-30
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S185090, C365S206000, C326S098000
Reexamination Certificate
active
06826090
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to latch circuitry and more particularly to radiation resistant latch circuitry.
2. Related Art
Domino logic latching circuits are known in the art. For example, the latch circuit
100
of
FIG. 1
shown here was disclosed in U.S. Pat. No. 5,896,046, “Latch structure for ripple domino logic,” Apr. 20, 1999, which is hereby incorporated herein by reference. Latch circuit
100
includes an input stage
10
and a feedback stage
120
. In
FIG. 1
, it is assumed that the data signal D_B comes from a preceding domino logic stage. During an evaluate phase the clock signal goes high and the data signal D_B is held high or driven low by the preceding domino logic stage. With the clock signal high, the latch circuit
100
permits the data signal to drive its latch node
121
high or low. Then, during a precharge phase, the data signal D_B goes high and the clock signal CLK goes low. According to the arrangement shown for circuit
100
, with the data and clock signals in their precharge states feedback through inverter
122
will keep the latch node
121
high or low regardless of whether the latch node was driven high or low during evaluation.
Another prior art domino latch circuit is the domino lookaside latch
200
shown in FIG.
2
. This circuit improves immunity to noise on the output node OUT by feeding forward to the output node from the inputs, data D_B and clock CLK, through circuit
100
and inverter
201
coupled to feed forward node
211
, instead of feeding back from the output node. (In FIG.
2
and other FIG's herein where circuit reference numbers
100
,
100
A,
100
B, etc. are shown it should be understood that such circuits are instances of circuit
100
shown in FIG.
1
. Likewise the same applies to circuit reference numbers
300
,
300
A, etc. being instances of circuit
300
shown in
FIG. 3.
)
Another prior art latch circuit
300
is shown in FIG.
3
. In this circuit
300
, cross coupled inverters
311
and
312
provide a memory cell
310
coupled to the latch node
301
, which provides output node OUT. A pair of parallel pass gates
320
controlled by the clock signal CLK and its complement CLK_B are interposed between the latch node
301
and a data signal IN. A single inverter
330
is interposed between the latch node
301
and the output node OUT. According to this arrangement, when the clock signal CLK is high the data signal IN drives the latch node
301
high or low, as the case may be, and when the clock signal is low the memory cell
310
keeps the latch node
301
high or low.
One problem with all these prior art arrangements is that cosmic rays and alpha particles can collide with a latch node and cause it and an output to switch states erroneously. One way that this has been addressed in the past has been to add charge on the latch node. While this solution tends to be effective to prevent erroneous switching caused by alpha particles, it is not very effective against cosmic rays, which have much higher energy.
Another way this has been addressed for a latch of the memory cell type is shown in
FIG. 4
, which was disclosed in IBM Technical Disclosure Bulletin, volume 30, No. 8, January 1988, Twice Redundant Radiation Hardened Latch, pages 248 through 249, and which is hereby incorporated herein by reference. According to this arrangement, three memory cell latch nodes B
1
, B
2
and B
3
are tied together to a single output inverter
401
via respective resistors
411
A,
411
B and
411
C. The resistors are necessarily rather large in order to be effective, so they tend to adversely affect performance of the circuit
400
. Therefore a need exists for improvements in radiation immunity for latches.
SUMMARY OF THE INVENTION
The foregoing need is addressed in the present invention. In one form of the invention, a radiation resistant latch has an overall output node, and first, second and third sublatches. The sublatches each have input circuitry, an output node coupled to the sublatch's input circuitry and feedback circuitry coupled to the sublatch's output node for reinforcing an output signal of the sublatch. The sublatches are operable to receive a data signal at their respective input circuitry and responsively generate binary-state output signals on their respective output nodes. The first and second sublatches are coupled to the third sublatch and the third sublatch has its output signal coupled to the overall output node such that if any one of the three sublatches is subjected to a radiation induced erroneous change of state, the output signals of the other two sublatches reduce an effect of the third sublatch feedback circuitry on an overall output signal for the latch.
Objects, advantages, additional aspects and other forms of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings.
REFERENCES:
patent: 4688219 (1987-08-01), Takemae
patent: 4942575 (1990-07-01), Earnshaw et al.
patent: 5162731 (1992-11-01), Fujimaki
patent: 5311070 (1994-05-01), Dooley
patent: 5338963 (1994-08-01), Klaasen et al.
patent: 5436572 (1995-07-01), Sugiyama
patent: 5508634 (1996-04-01), Sugiyama
patent: 5600260 (1997-02-01), LaMacchia et al.
patent: 5896046 (1999-04-01), Bjorksten et al.
patent: 6046606 (2000-04-01), Chu et al.
patent: 6275080 (2001-08-01), Phan et al.
patent: 6339550 (2002-01-01), Wanlass
patent: 6348356 (2002-02-01), Shabde et al.
patent: 6696873 (2004-02-01), Hazucha et al.
patent: 63-197113 (1988-08-01), None
“Soft-Error Free Differential ECL Latch,” IBM Technical Disclosure Bulletin, vol. 32, No. 7, Dec. 1989, pp. 73-74.
Weaver, H.T., et al., “Soft Error Protection using Asymmetric Response Latches,” IEEE Transactions on Electron Devices, vol. 38, No. 6, Jun. 1991, pp. 1555-1557.
J.A. Hoffman, “Twice Redundant Radiation Hardened Latch,” IBM Technical Disclosure Bulletin, vol. 30, No. 8, Jan. 1988, pp. 248-249.
D.B. Eardley, “Latch Circuit Insensitive to Disturb by Alpha Particles,” IBM Technical Disclosure Bulletin, vol. 24, No. 12, May 1982, pp. 6461-6462.
D.L. Arlington, et al., “On-Chip Logic Enhancements for Test of Error Checking and Correcting Related Functions in On-Card Applications,” IBM Technical Disclosure Bulletin, vol. 30, No. 12, May 1988, pp. 247-250.
Chu Sam Gat-Shang
Klim Peter Juergen
Lee Michael Ju Hyeok
Paredes Jose Angel
Elms Richard
England Anthony V.S.
McBurney Mark E.
Nguyen Tuan T.
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