Apparatus and method for a one-phase write to a...

Static information storage and retrieval – Systems using particular element – Semiconductive

Reexamination Certificate

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C365S189011, C365S189020

Reexamination Certificate

active

07075821

ABSTRACT:
A method and apparatus for a one-phase write to a one-transistor memory cell array. In one embodiment, the method includes a one-phase write to a selected wordline of a memory cell array. Once the wordline is selected, a logical zero value is stored within at least one memory cell of the selected wordline of the memory cell array. Simultaneously, a logical 0 value is stored within at least one memory cell of the selected wordline of the selected memory cell array. Other embodiments are described and claimed.

REFERENCES:
patent: 6906953 (2005-06-01), Forbes
Ohsawa, Takashi et al., “Memory Design Using a One-Transistor Gain Cell on SOI”,IEEE Journal of Solid-State Circuits,vol. 37, No. 11, Nov. 2002, pp. 1510-1522.
Yoshida, Eiji et al., “A Design of a Capacitorless IT-DRAM Cell Using Gate-induced Drain Leakage (GIDL) Current for Low-power and High-Speed Embedded Memory”, 2003 IEEE, 4 pp.

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