Apparatus and method configured to lower thermal stresses

Details Apparatus and method configured to lower thermal stresses Apparatus and method configured to lower thermal stresses

2011-02-15

2011-02-15

Zarneke, David A (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With stress relief

C257SE23019

Reexamination Certificate

active

07888782

ABSTRACT:
An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a lead frame and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the lead frame. The buffer layer includes a material, which is soft in comparison to a material of the diffusion solder layer, and includes a layer thickness such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range.

REFERENCES:
patent: 5025114 (1991-06-01), Braden
patent: 5386141 (1995-01-01), Liang et al.
patent: 5506446 (1996-04-01), Hoffman et al.
patent: 7061085 (2006-06-01), Moxham
Callister, Jr., William D. Materials Science and Engineering, 1994, John Wiley & Sons, Inc., Third Edition, p. 122.
“Elastoplastic Creep Analysis of Thermal Stress and Strain in Aluminum Interconnects of LSIs”, Kazunori Hiraoka, Electronics and Communication in Japan, Part 2, vol. 77, No. 3, 1994.
“Mechanical Properties of Electroplated Copper Thin Films”, R. Spolenak, et al., Materials Research Society Symp. Proc. vol. 594, 2000 Materials Research Society.
“Mechanical Stess as a Function of Temperature in Aluminum Films”, Donald S. Gardner, et al., IEEE Transaction on Electronic Devices, vol. 35, No. 12, Dec. 1988.
“Stress evolution in passivated thin films of Cu on silica substrates”, Y-L. Shen, et al., J. Materials Research Society, vol. 13, No. 7, Jul. 1998.
“Thermo-Mechanical Design of Flip Chips for Harsh Environments”, Stelios Michaelides, et al., ICEMCM '96 Proceedings, International Conference of Multichip Modules, Apr. 17-19, 1996.

Affiliated with

Also associated with

Rating

Apparatus and method configured to lower thermal stresses does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus and method configured to lower thermal stresses, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method configured to lower thermal stresses will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2635069