Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-06-29
2003-07-29
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S239000, C438S243000, C438S244000, C438S252000, C438S600000, C438S601000, C438S131000, C438S132000, C257S104000, C257S577000, C257S594000, C365S105000, C365S208000, C365S243000, C365S165000, C365S175000
Reexamination Certificate
active
06599796
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention pertains to the field of memory cell arrays. More particularly, this invention relates to memory structure and fabrication processes for reducing crosstalk between memory cells in a cross point memory array.
2. Background
Portable consumer devices are becoming more compact yet increasingly sophisticated, requiring inherent structure to generate and/or utilize increasing quantities of data. Digital devices, such as digital cameras, may require at least hundreds of megabytes (MB) of data storage either built into or attachable to the camera. To satisfy the needs of this type of data storage application, future storage memories should be relatively low in cost, extremely compact and have capacities of around 100 MB to one gigabyte (GB). The storage memory should also be low in power consumption, less than one watt, and have relatively rugged physical characteristics to cope with the portable battery-powered operating environment.
For archival storage, data need only be written to the memory once. Preferably, the memory should have a short access time, on the order of milliseconds, and a moderate transfer rate, such as one to two MB per second. Preferably, the storage memory should be capable of interfacing with a wide variety of industry standard platforms and modules.
An application for meeting this demand involves the use of write-once cross point memory devices. In cross point memory arrays, a matrix of memory elements are formed, each comprising a fuse or anti-fuse and a diode connected in series. The memory elements are formed by a plurality of semiconductor and passivation layers disposed between conductive lines or electrodes.
One application for utilizing write-once cross point memory arrays to provide high density archival storage in portable devices is described in co-pending U.S. patent application Ser. No. 09/875,356, filed Jun. 5, 2001, entitled “Write-Once Memory”, the disclosure of which is incorporated herein by reference. The memory system disclosed therein, referred to as portable inexpensive rugged memory (PIRM), provides high capacity write-once memory at low cost for archival storage. This result is realized in part by avoiding silicon substrates, minimizing process complexity and lowering area density. The memory system includes a memory module formed of a laminated stack of integrated circuit layers constructed on plastic substrates. Each layer contains a cross-point diode memory array. Sensing of the data stored in the array is carried out from a separate integrated circuit remote from the memory module.
Because PIRM memory is relatively inexpensive, users will likely accumulate a large number of PIRM modules with a variety of stored content. It is important to be able to fabricate and assemble memory modules by a straightforward and relatively inexpensive process to minimize the need for precision while maximizing information storage density and simplifying addressing, reading and writing functions.
In layered high-density memory modules, such as described above, the potential for current leakage or “crosstalk” between adjacent memory cells is substantially increased. This problem can result in intolerable increases in error rates and power loss as current leaks between “on” and “off” memory cells, as well as along other potential crosstalk paths.
In
FIG. 1
, three schematic diagrams illustrate likely paths for leakage current, where the cross point diodes are formed by orthogonal electrode strips having amorphous silicon p-i-n layers between the strips and the anti-fuse is made by interfacing intrinsic amorphorous silicon with a metal with the ability to diffuse into the semiconductor to form a good contact, a “diffusive metal”. In
FIG. 1A
, a grid of cross point memory electrodes
10
is shown. The bottom electrode strips
12
-
14
in the X direction are orthogonal to the top electrode strips
15
-
17
in the Y direction. The bottom electrode strips
12
to
14
are made of a conducting material, preferably metal, and the top electrode strips
15
-
17
are made of diffusive metal, such as silver. Alternate positive voltages,
+
V, and negative voltages,
−
V, are imposed on alternate electrode strips in both directions, as shown.
FIG. 1B
is a cross-sectional view along the X axis of the central bottom X electrode
13
having a negative voltage,
−
V thereon. Top electrode
15
has negative voltage
−
V voltage, electrode
16
has a positive voltage,
+
V voltage and electrode
17
has a negative voltage,
−
V. Diodes
20
-
22
are formed between electrodes
15
-
17
and electrode
13
by three semiconductor p-i-n layers
23
-
25
deposited on electrode
13
. A p
+
-doped layer
23
is deposited above an intrinsic i layer
24
which in turn overlays a n
+
-doped layer
25
. Anti-fuses
26
-
28
are formed by a passivation layer
29
formed above diodes
20
-
22
and beneath the top electrodes
15
-
17
.
A p
+
-doped layer is a semiconductor material such as silicon heavily doped with a p-type dopant, such as boron. Similarly an n
+
-doped layer is a semiconductor material such as silicon that is heavily doped with an n-type dopant, such as phosphorous. The “+” designation indicates that the material has been heavily doped to at least 1% concentration.
Bit-to-bit crosstalk occurs when an anti-fuse of an addressed element is open (without conducting connection) while a neighboring anti-fuse is conducting. One leakage path is from a conducting anti-fuse to the nearest neighbor diode. As shown in
FIG. 1B
, when anti-fuse
26
is conducting, a leakage current
25
flows from anti-fuse
26
through the p+-layer
23
to neighboring diode
21
. The leakage current through the p+-layer is small since the p+-layer is usually very thin, on the order of 20 nanometers.
FIG. 1C
is a cross-sectional view along the Y axis of the central top electrode
16
having a positive voltage,
+
V thereon. Bottom electrode
12
has a positive voltage,
+
V, electrode
13
has a negative voltage,
−
V, and electrode
14
has a positive voltage,
+
V, imposed thereon. Anti-fuses
31
-
33
are formed by electrode
16
and passivation layer
29
. Diodes
34
-
36
are formed by p-i-n layers
23
-
25
and electrodes
12
-
14
. When anti-fuse
31
is conducting, leakage current
37
can flow through p+-layer
23
to neighboring diode element
35
. Again, since the p+-layer
23
is quite thin, the leakage current
37
is small. However, the leakage current
38
through the n
+
layer
24
, from electrode
14
of diode
34
to electrode
13
of diode
35
, is large and can be a significant factor. The n-type layers are usually thicker and have substantially less resistance than p
+
layers. In addition, electron mobility is greater than hole mobility, so current leakage is usually greater in n
+
-layers than in p
+
-layers.
Leakage current increases with the size of a memory array.
FIG. 2
shows a graph giving estimated leakage current (1.E-0X means 10
−x
amps) as a function of memory array size (1.E+0Y means 10
+y
bits of memory). The estimations in the graph assume that the resistivity of phosphorous-doped amorphous silicon is about one kilo-ohm centimeter (K&OHgr;-cm), the thickness of the n
+
layer is 100 nanometers, the voltage differences across the electrodes is 5 volts, and the line width equals the line spacing. When the size of a memory array exceeds one megabit (10
+6
memory cells), the leakage current is greater than 0.1 milliamp (10
−4
amps), which is unacceptable for a memory array. This point is illustrated in
FIG. 2
at point
39
. At the present time, consumer units having at least 8 megabytes (64 megabits) of memory are not unusual. Thus, leakage current is a major problem in both existing and future memory arrays.
Others have attempted to construct various means for minimizing current leakage in memory arrays. One such structure is sho
Beck Patricia A.
Mei Ping
Taussig Carl P.
Lee Jr. Granvill D
Smith Matthew
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