Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-08-25
2001-10-09
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700, C365S230020, C365S230080
Reexamination Certificate
active
06301164
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to semiconductor memory devices, and in particular to repairing columns in a memory device.
BACKGROUND OF THE INVENTION
Semiconductor memory devices such as dynamic random access memory (DRAM) devices are widely used to store data in computers and electronic products. A DRAM device typically has a large number of memory cells to store the data. The memory cells are typically arranged in rows and columns.
To ensure the reliability of the memory device, each of the memory cells is tested to determine its performance or to detect a defective cell. Typically, to repair a column having a defective cell, the entire column must be replaced by a spare column or redundant column within the memory device. The redundant column has the same number of cells as that of the column having the defective cell. This method for the repair of a column of a memory device is not cost effective or efficient, since not only the defective cell with the column is replaced but good cells within the same column are also replaced. Also, providing an entire redundant column consumes valuable space in the memory device.
Thus, there is a need for a better method to repair a column having a defective cell.
SUMMARY OF THE INVENTION
The problems associated with repairing column having a defective memory cell and other problems are addressed by the present invention and will be understood by reading the following disclosure. An antifuse method to repair a column of a memory device is provided. The method more efficiently repairs a column of a memory device than previous methods.
In one embodiment, an integrated circuit is provided. The integrated circuit includes a first set of programmable elements programmed to store an address of a column having a bad memory cell, and a second set of programmable elements programmed to store a segment-in-time (SIT) of the bad memory cell, the SIT of the bad memory cell indicating a relative position of the bad memory cell within a plurality of memory cells being accessed in a memory access. The SIT allows the memory device to selectively repair a bad memory cell within a column of memory cells accessed during a memory operation.
In another embodiment, a method of repairing a column of a memory device having a bad cell is provided. The method includes programming a first set of programmable elements to store an address of a column having a bad cell. The method also includes programming a second set of programmable elements to store a segment-in-time (SIT) information of the bad cell indicating a relative position of the bad memory cell within a plurality of memory cells being accessed in a previous memory access. The method further includes decoding the SIT information to generate an SIT signal to replace the bad memory.
REFERENCES:
patent: 5642316 (1997-06-01), Tran et al.
patent: 5732030 (1998-03-01), Dorney
patent: 5798974 (1998-08-01), Yamagata
patent: 6097644 (2000-08-01), Shirley
patent: 6154398 (2000-11-01), Cutter et al.
Batra Shubneesh
Manning Troy A.
Martin Chris G.
Morgan Donald M.
Dinh Son T.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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