Anti-punchthrough ion implantation for sub-half micron channel l

Details Anti-punchthrough ion implantation for sub-half micron channel l Anti-punchthrough ion implantation for sub-half micron channel l

1996-03-11

1997-03-25

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 44, 437 67, H01L 21762

Patent

active

056144300

ABSTRACT:
A method for forming a MOSFET device, with reduced exposure to source and drain leakage currents, that can arise due to a junction depletion punchthrough phenomena, has been developed. An anti-punchthrough, ion implantation, is performed in a confined area below the channel region. The ability to confine the area used for the anti-punchthrough region, results in protection against leakage, however with only a minimum of parasitic capacitance increase. The confined, anti-punchthrough region is obtained via ion implantation procedures into a channel region, using polysilicon sidewalls for purposes of placing the implanted region only into desired regions below the channel region.

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patent: 5489543 (1996-02-01), Hong
S. Wolf, "Silicon Processing For The VLSI Era-vol. 1", Lattice Press, Sunset Beach, CA, 1995, pp. 232-239.

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