Anti-fuse memory cell with asymmetric breakdown voltage

Details Anti-fuse memory cell with asymmetric breakdown voltage Anti-fuse memory cell with asymmetric breakdown voltage

2001-12-20

2004-03-09

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having fuse element

C257S528000, C257S529000, C257S530000

Reexamination Certificate

active

06704235

ABSTRACT:

BACKGROUND
This invention relates to anti-fuse memory cells, and in particular to improved anti-fuse memory cells that are more resistant to unintended anti-fuse rupture.
A memory array conventionally includes a two-dimensional or three-dimensional array of memory cells. One type of known memory cell includes an anti-fuse layer and diode components in each memory cell. Individual memory cells are interconnected between conductors, often known as word lines and bit lines. The anti-fuse layer is initially intact, but it can be ruptured or broken by applying a sufficient voltage across the memory cell. For example a write signal Vpulse is applied across a memory cell at the intersection of selected word lines and bit lines, and this write signal is maintained for a time Tpulse. The values of Vpulse and Tpulse are chosen such that the anti-fuse layer ruptures, and a high conductivity state of the memory cell is established. For many anti-fuse materials, the relation between Tpulse and Vpulse required for anti-fuse rupture is such that if Vpulse is increased, Tpulse can be decreased, and vice versa.
When the programming pulse Vpulse is applied to the selected memory cell, it is important to control the voltage applied across unselected cells to ensure that current leakage through these unselected cells does not lead to unintentional rupture of the unselected anti-fuse layers, or to an excessive voltage drop in the selected word and bit lines before the selected anti-fuse layer has ruptured. The voltage Vclamp across the memory cells at the intersection of two unselected lines (unselected cells) during the programming pulse can be a substantial fraction of Vpulse. The clamp voltage Vclamp is applied in the reverse bias direction across unselected cells during programming of each selected cell. Hence, an unselected cell should be capable of enduring Vclamp without rupture of the unselected anti-fuse layer for a time period substantially longer than Tpulse (depending upon the size of array).
SUMMARY
By way of general introduction, the preferred embodiments described below include a memory cell including an anti-fuse layer and two diode components, wherein the anti-fuse layer ruptures at a higher reverse-bias voltage than forward-bias voltage. In these embodiments, the anti-fuse layer provides a relatively high anti-fuse current leakage density prior to anti-fuse rupture. Preferably, the anti-fuse current leakage density matches the diode current leakage under reverse bias. Poly silicon diodes have a higher leakage than single-crystal diodes due to carrier generation in the depletion region. For this reason, unruptured anti-fuse layers used with poly silicon diode components preferably are characterized by a high conductivity or leakage current density. This can be achieved by using an anti-fuse layer with a thickness below a predetermined value or by forming the anti-fuse layer from materials with high current leakage rates prior to anti-fuse rupture.
The foregoing sections have been provided by way of general introduction, and they are not intended to narrow the scope of the following claims.


REFERENCES:
patent: 5565703 (1996-10-01), Chang
patent: 5573970 (1996-11-01), Pramanik et al.
patent: 6251710 (2001-06-01), Radens et al.
patent: 6420215 (2002-07-01), Knall et al.
de Graaf et al., “A Novel High-Density Low Cost Diode Programmable Read Only Memory,” IEDM Tech. Dig., pp. 7.6.1-7.6.4 (1996).
“Anti-Fuse Memory Cell with Asymmetric Breakdown Voltage,” U.S. patent application Ser. No. 09/918,307, filed Jul. 30, 2001; Inventors: N. Johan Knall, Igor G. Kouznetsov, and Michael A. Vyvoda.
Office Action Directed Against U.S. patent application Ser. No. 09/918,307, 6 pages, Oct. 4, 2002.

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