Anneal technique for reducing amount of electronic trap in...

Details Anneal technique for reducing amount of electronic trap in... Anneal technique for reducing amount of electronic trap in...

1997-12-19

2001-02-13

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S017000, C438S261000, C438S902000, C438S904000

Reexamination Certificate

active

06187632

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an anneal technique for reducing an amount of electronic trap in a gate oxide film of a transistor, which is applied to a semiconductor device using an insulating film, which is formed by a chemical reaction of gas as material, as a passivation film.
A passivation film, which is formed of SiO
2
, Si
3
N
4
, or SiO
x
N
y
(x, y denote arbitrary positive numbers each showing an atomic ratio), is often used in LSI. As an interlayer insulating film of a lower layer of the passivation film, there is used an insulating film of silicon glass series such as PSG, BPSG, ASG, BSP, CSG, etc.
The insulating film used as a passivation film has low hygroscopicity and water permeability, and the insulating film used as an interlayer insulating film has a property of easily absorbing water. The interlayer insulating film contains water permeated mainly in manufacturing the interlayer insulating film.
Water molecules in the interlayer insulating film is dispersed in the interlayer insulating film by heat generated in depositing the passivation film. At this time, water molecules neither transmit through the passivation film nor disperse to the outer portion of the semiconductor device. Water molecules disperse into the gate oxide film of the transistor in the semiconductor device. The reason is that the passivation film has a property of permeating water with difficulty (low water permeability).
Water molecules permeated into the gate oxide film of the transistor cause electronic trap in the gate oxide film so as to deteriorate a hot carrier life of the transistor.
To solve the above problem, for example, there is an anneal method for the purpose of removing water of the interlayer insulating film before depositing the passivation film. For example, this method is a well-known technique as disclosed in Japanese Patent Application KOKAI Publication No. 61-219141.
However, in this method, the anneal process must be performed in a cleaning room since the annealing is performed before depositing the passivation film. As a result, the manufacturing cost is increased.
Japanese Patent Application KOKAI Publication No. 61-219141 also discloses removal of water of the interlayer insulating film in a DRAM (dynamic random access memory). To reduce a failure ratio of pose-failure of DRAM, anneal temperature and time may be set to 350° C. and one hour before forming the passivation film (plasma nitrogen film) as described in the above publication.
However, even if the conditions disclosed in the above publication are directly applied to a nonvolatile semiconductor memory such as EEPROM, the electronic trap in the gate oxide film of the memory cell transistor cannot be reduced to an extent that sufficient reliability can be obtained.
In other words, in the nonvolatile semiconductor memory such as EEPROM, it is necessary to review annealing temperature and time in more detail.
Thus, conventionally, the passivation film is formed to prevent water and impurity materials from being permeated from the outer portion of the semiconductor device (LSI). Due to this, the passivation film is formed of material having low hygroscopicity and water permeability. Since the water permeability of the passivation film is low, water of the interlayer insulating material disperses into the gate oxide film of the memory cell transistor to cause electronic trap.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of manufacturing a passivation film to prevent water of an interlayer insulating film from dispersing into a gate oxide film of a memory cell transistor even if a passivation film is formed of material having low hygroscopicity and water permeability, that is, material having high moisture vapor resistance, thereby improving reliability of the memory cell transistor.
To attain the above object, according to the semiconductor device manufacturing method of the present invention, annealing is performed after forming a passivation film covering an upper portion of a semiconductor substrate on which a transistor is formed.
In this case, an amount of electronic trap in a gate insulating film of the transistor is monitored after annealing, and annealing is performed again when the amount of electronic trap exceeds a predetermined value.
The annealing is performed under at least one of conditions of temperature exceeding 350° C. and time exceeding 60 minutes. Also, the annealing is performed at temperature below a melting point of the metallic wire formed at a lower portion of the passivation film.
The annealing is performed under a condition satisfying the following equation:
t
≧7.86×10
−11
×L
2
×exp (9115
/T)
where t is anneal time (minutes), L is a thickness (nm) of the passivation film, and T is anneal temperature (absolute temperature).
The annealing may be performed just after the passivation film is formed. Also, the annealing may be performed after the passivation film is formed and an opening is formed to expose a bonding pad onto the passivation film.
The annealing may be performed under pressure lower than atmosphere.
The transistor is a transistor constituting a memory cell of a semiconductor memory.
The passivation film is one insulating film selected from silicon oxide, silicon nitride and silicon oxynitride, and the passivation film is formed by CVD. Also, the passivation film is formed such that its refractive index is 1.65 or more.
An interlayer insulating film of silicon glass series, is formed at the lower portion of the passivation film. Water in the interlayer insulating film is discharged to an outer portion of the passivation film by the anneal.
Moreover, to attain the above object, the semiconductor manufacturing method comprises a step of annealing before forming a passivation film, which covers the upper portion of a semiconductor substrate having a transistor formed. The annealing is performed under a condition satisfying the following equation:
t
≧7.86×10
−5
×exp (9115
/T)
where t is anneal time (minutes), and T is anneal temperature (absolute temperature).
The annealing step and the passivation film forming step are continuously performed in one apparatus to prevent water and impurity material from being permeated again.
Also, an amount of electronic trap in a gate insulating film of the transistor is monitored after annealing, and the annealing may be performed again when the amount of electronic trap exceeds a predetermined value.
The annealing is performed under at least one of conditions of temperature exceeding 350° C. and time exceeding 60 minutes.
The annealing is performed at temperature below a melting point of the wire formed at the lower portion of the passivation film.
The annealing may be performed under pressure lower than atmosphere. The transistor is a transistor constituting a memory cell of a semiconductor memory.
The passivation film is one insulating film selected from silicon oxide, silicon nitride and silicon oxynitride, and the passivation film is formed by CVD. The passivation film is formed such that its refractive index is 1.65 or more.
An interlayer insulating film of silicon glass series, is formed at the lower portion of the passivation film. Water in the interlayer insulating film is discharged to an outer portion of the passivation film by the annealing.
Furthermore, to attain the above object, the semiconductor device manufacturing method of the present invention comprises the steps of forming a first passivation film, which covers the upper portion of a semiconductor substrate having a transistor formed, annealing after forming the first passivation film, and forming a second passivation film, having high moisture vapor resistance higher than the first passivation film, on the first passivation film.
The manufacturing method further comprises a step of monitoring an amount of electronic trap in a gate insulating film of the transistor just after annealing. Then, the annealing is performed again when the amount of electroni

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