Anisotropic formation process of oxide layers for vertical...

Details Anisotropic formation process of oxide layers for vertical... Anisotropic formation process of oxide layers for vertical...

2001-10-09

2002-08-06

Thompson, Craig (Department: 2813)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

By reaction with substrate

Reexamination Certificate

active

06429148

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a formation process of an oxide layer, and especially to an anisotropic formation process of an oxide layer in a trench.
BACKGROUND OF THE INVENTION
The semiconductor memory, such as a Dynamic Random Access Memory (DRAM), is usually composed of multiple memory units with storage nodes. The DRAM nowadays generally adopts a trench construction to improve capacitance in shrank memory units. The storage node is accessed through an access transistor, e.g. a vertical transistor, to allow the charge being stored into or retrieved form the storage node. The storage node of memory must be electrically isolated from the gate conductive layer.
A conventional method for ensuring electrical isolation of the storage node is forming a trench top isolation layer over the storage node. The storage node usually includes a trench partially filled with polysilicon. An oxide layer, usually a silicon dioxide, is deposited on the surface of the semiconductor device and also on the aforesaid polysilicon material. The oxide layer on the semiconductor device, except that in the trench, is removed by planarizing the surface. Afterwards, the oxide layer in the trench is etched and a predetermined thickness thereof remains. However, the oxide layer alone may not provide sufficient and reliable electrical isolation. Additionally, the oxide layer etching can not be controlled easily and the thickness of the residual oxide layer varies substantially. It is noted the substantial thickness variation of the remained oxide layer is not allowed in DRAM manufacturing processes.
When a vertical transistor is fabricated in a memory device, a buried strap portion of the storage node, which is under the top trench oxide, must diffuse out and electrically connect to the vertical transistor channel. Therefore, if the transistor is “ON”, a bitline electrically connects with the storage node. The channel must electrically isolate from the gate conductive layer through an insulating layer. The insulating layer is usually formed by partially oxidizing polysilicon of the gate oxide layer in the trench.
Many prior art works in this field, such as U.S. Pat. No. 6,184,091 issued to Gruening et al. entitled “Formation of Controlled Trench Top Isolation Layers for Vertical Transistors”, are disclosed. Please refer to
FIG. 1
a
, a semiconductor device
100
has a substrate
101
, a pad oxide layer
102
and a pad nitride layer
103
thereon. A trench
104
is formed deep into the substrate
101
, the pad oxide layer
102
and pad nitride layer
103
. A collar
105
is formed in the trench
104
for electrically isolating a portion of trench
104
from the substrate
101
. The trench
104
is partially filled with a conductive filler material
106
. The filler material
106
extends over the top portion of collar
105
and contacts with the substrate
101
. Therefore, a buried strap
108
is formed in the trench. A recess
107
remains at the top of the trench
104
. Looking at the recess
107
, the recess
107
includes a bottom surface
109
and a circumferential wall
110
. The bottom surface
109
is the top surface of buried strap
108
.
Please refer to
FIG. 1
b
, the trench top oxide formation starts with a nitride liner
111
formed on the circumferential wall
110
. The nitride liner
111
formation is first deposited a nitride liner
111
on the pad nitride layer
103
, bottom surface
109
and circumferential wall
110
. The nitride liner
111
is preferably a silicon nitride. Then, the nitride liner
111
is removed from all surfaces except the circumferential wall
110
. A sub-atmospheric chemical vapor deposition (SACVD) layer
112
is then deposited. The SACVD layer is usually an oxide or an ozone rich TEOS (tetraethoxysilane) layer. The SACVD layer
112
grows at a rate of about 5 times greater on silicon than on nitride. Therefore, the thickness of the SACVD layer
112
is about 5 times thicker on the bottom surface
109
than on the pad nitride layer
103
and circumferential wall
110
. Accordingly, it is easy that the SACVD layer
112
on the pad nitride layer
103
and circumferential wall
110
are removed, and on the bottom surface
109
remains the SACVD layer
112
of reduced thickness, as shown in
FIG. 1
c
. In the succeeding processes, the nitride liner
111
is removed and an oxide layer
113
is formed to serve as a gate oxide on the circumferential wall
110
, as shown in
FIG. 1
d.
As mentioned above, the fabrication process of a trench top oxide is complicated. The steps of first depositing the SACVD layer
112
, and then etching have multiple variables to control while etching such that stability is low. Before forming the gate oxide
113
, the nitride linear
111
must be removed in advance. To improve yield, and to decrease number of steps, it has a demand for a new method for forming trench top oxide and gate oxide with less steps and higher yield.
SUMMARY OF THE INVENTION
An objective of the present invention is to provide a method for forming a trench top oxide and a gate oxide in fewer steps.
Another objective of the present invention is to provide a method for forming the trench top oxide and gate oxide at the same time.
The method of the present invention is to form a thick oxide layer on a bottom surface of a recess and a thin oxide layer on a circumferential wall of the recess. The recess is part of a trench formed in a substrate, and the circumferential wall is perpendicular to the bottom surface. The method includes steps as follows. Inert gas ions are implanted into the bottom surface of the recess at a direction parallel to the circumferential wall. Afterwards, the substrate is thermally processed by using a thermal oxidation process to form a thick oxide layer on the bottom surface and a thin oxide layer on the circumferential wall.


REFERENCES:
patent: 6184091 (2001-02-01), Gruening et al.
patent: 6204109 (2001-03-01), Wu

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