Angled implant to build MOS transistors in contact holes

Details Angled implant to build MOS transistors in contact holes Angled implant to build MOS transistors in contact holes

1999-06-15

2001-11-13

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S301000, C438S302000, C438S576000

Reexamination Certificate

active

06316318

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to fabricating integrated circuits, and more specifically, to a method for fabricating a metal-oxide-semiconductor (MOS) transistor.
2. Discussion of the Related Art
FIGS. 1 through 4
illustrate a sequence of steps in a CMOS process. In particular,
FIG. 1
shows an epitaxial region
106
on semiconductor substrate
100
. Semiconductor substrate
100
can be, for example, a p-type monocrystalline semiconductor, with a thin (5-10-&mgr;m thick), lightly doped P-type epitaxial layer
106
at the surface
An N-well region (e.g., N-well region
104
) is typically provided in epitaxial layer
106
in an “active” region (i.e., where a transistor can be fabricated). To form N-well region
104
, a thin oxide
102
(e.g., typically 100-500 Åthick) is grown on epitaxial layer
106
. A silicon nitride (SiN) layer
108
is then deposited, patterned and etched. Then, as shown in
FIG. 2
, a LOCalized Oxidation of Silicon (LOCOS) process is carried out. The exposed portions of the semiconductor surface (i.e., those portions not protected by silicon nitride layer
108
) are oxidized to form a thick thermal oxide (“field oxide”)
114
. The portions of semiconductor surface with thermal oxide
114
is referred to as the field regions. The portions of the semiconductor surface protected by silicon nitride layer
108
become the active regions, where active semiconductor devices are to be fabricated. Thermal oxide
114
isolates devices in active regions from each other. Silicon nitride layer
108
is then removed.
After a masking step creating mask
112
, an ion implantation step
116
is carried out through mask
112
to form N-well region
104
. Phosphorus or arsenic can be used to form an N-well while boron or BF
2
+
can be used to form a P-well. The impurities are then driven in to the appropriate depth during subsequent high temperature cycles. At the conclusion of the drive-in processes the surface concentration in N-well region
104
can be ~1×10
16
/cm
3
and the surface concentration in a typical P-well is ≦1×10
15
/cm
3
. The mask is then removed from the active regions, as shown in
FIG. 3
(prior art). NMOS devices can be formed in epitaxial layer
106
or in P-wells, while the PMOS devices are formed in doped (e.g., 1×10
16
/cm
3
) N-well region
104
. A threshold adjust implant can then be carried out, followed by growing of a gate oxide.
Polysilicon is deposited by CVD as a material for forming gate electrodes. The polysilicon layer is subsequently doped to form a polysilicon gate material. Polysilicon can be doped either by diffusion or by ion implantation after deposition, or in situ during deposition. The polysilicon is then patterned to form polysilicon gates, such as those designated by reference number
116
in
FIG. 4
(prior art).
Next, polysilicon gates
116
are used as a mask to selectively implant the source/drain regions
120
of the transistors. Each of polysilicon gates
116
protects the channel region under the gate from being implanted by dopants
118
. Arsenic is the preferable dopant for the n+ source/drain regions (NMOS devices), so that shallow junctions and minimum lateral diffusion under the gate can be obtained. Arsenic is typically implanted to a dose of 3-6×10
15
cm
−2
, and with an energy of 40-60 keV. Boron is often implanted as BF
2
+ for the p+ region (for shallow junction formation) at doses of 1-5×10
15
cm
−2
and energies of 30-50 keV. These implants are usually performed through a screen oxide to protect source/drain regions
120
from contamination during the implant procedure. These implants are then annealed with a short thermal process at a temperature ranging from 800-1100° C.
In the above-described conventional CMOS process, the implant area is generally defined by an oxide or other masking material opening on the surface of the silicon. The size of this opening is determined by the resolution of the photoresist process which can be limited by many aspects of the process, including hardware (e.g. diffraction of light, lens aberrations, and mechanical stability of the system); optical properties of the resist material (e.g. contrast, swelling behavior, and thermal flow); and process characteristics (e.g. softbake step, develop step, postbake step, and etching step). Thus, the size for the diffusion regions which are the source and the drain of the transistor are limited by the photoresist process.
A process for fabricating an MOS transistor having a narrow diffusion region smaller than the resolution of a photo resist process, using conventional CMOS fabrication techniques, is desired.
SUMMARY OF THE INVENTION
A method for forming a MOS transistor having a narrow diffusion region that is smaller than the diffusion region produced by a photoresist process is described herein which utilizes standard CMOS processing. In one embodiment, LOCOS provides a standard isolation structure, such as a shallow trench. The surface of the isolation structure is then cleaned. A polysilicon layer is then deposited and doped either n+ or p+ selectively. The polysilicon layer is then patterned. Next, a dielectric layer is deposited over the doped polysilicon layer. A refractory metal layer is then deposited over the dielectric layer. Next, a contact hole with a high aspect ratio is defined in the oxide where the transistor is to be formed. Angled implant to form lightly doped drain (LDD) structures, or alternatively, graft source/drain structures, are carried out from two opposite sides only. The refractory metal layer is then removed. The surface of the wafer is cleaned and the implant is activated. Sidewall spacers are then formed in the contact hole. A gate oxide layer is either thermally grown or deposited in the contact hole. The remainder of the contact hole is then filled with a gate material to form a gate electrode. Next, the gate material is polished so that the top of the gate is coplanar with the dielectric layer. In another embodiment, a gate oxide layer is grown before deposition of the spacer material.
The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.


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