Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2006-11-28
2006-11-28
Corrielus, Jean B. (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C327S156000
Reexamination Certificate
active
07142624
ABSTRACT:
The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the transmitter portion and receiver portion comprising a phase locked loop (PLL) circuit. The PLL circuit comprises a voltage control oscillator, a frequency divider, a phase-frequency detector, a charge pump and a multi-pole loop filter. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop.
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Cranford, Jr. Hayden Clavie
Garvin Stacy Jean
Norman Vernon Roberts
Owczarski Paul Alan
Schmatz Martin Leo
Cockburn Joscelyn G.
Corrielus Jean B.
Daugherty Patrick J.
Driggs, Hogg & Fry Co., Ltd.
International Business Machines - Corporation
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