Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-03-30
2004-01-20
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S740000, C327S056000, C327S072000
Reexamination Certificate
active
06681355
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an integrated circuit system with analog boundary scan capabilities.
An electronic unit has further reduced its size and weight along with recent upsurge in number of electronic components integrated together within the electronic unit. Such a densely packed and miniaturized electronic unit, however, also has a downside. For example, the smaller the electronic unit, the more difficult it is to test the unit.
To make such a unit testable more easily, a test system called “analog boundary scan (ABS) test system” was proposed in compliance with the IEEE standard No. P1149.4. In the ABS test system, a tester is provided within each integrated circuit to test the performance of the integrated circuit itself or interconnection with other integrated circuits on a circuit board after the circuits have been mounted on the board.
The IEEE P1149.4 standard recommends that an integrated circuit should be tested by simply checking interconnection among integrated circuits including the one under the test. For that purpose, a logic circuit should be provided within the integrated circuit to detect potentials at respective connection terminals. Specifically, this method is carried out in the following manner.
FIG. 7
illustrates one of known ABS compliant integrated circuit systems. As shown in
FIG. 7
, an interconnect
3
is provided to connect two integrated circuits
1
and
2
together. A digital or analog signal, which is output from a driver
6
included in the integrated circuit
2
, is passed through a terminal
5
, the interconnect
3
and another terminal
4
and then transmitted to a receiver
7
included in the integrated circuit
1
. A logic circuit
51
, the input of which is connected to the terminal
4
to check how the interconnect
3
is connected by detecting a potential at the terminal
4
, is also provided for the integrated circuit
1
. In the example illustrated in
FIG. 7
, the logic circuit
51
is implemented as a CMOS inverter
51
applying a predetermined threshold voltage to the terminal
4
.
In
FIG. 7
, the interconnect
3
is tested by getting respective voltages, which are higher and lower than the threshold voltage applied from the logic circuit
51
, output from the driver
6
and making the logic circuit
51
check whether or not these output voltages are received at the terminal
4
as expected. In this specification, these voltages, which are higher and lower than the input threshold voltage, will be called “H-level” and “L-level” voltages, respectively.
First, suppose the H-level voltage is output from the driver
6
. In this case, if the interconnect
3
is connected normally, then the H-level voltage is transmitted to the terminal
4
and the logic circuit
51
receives and inverts the H-level voltage at the terminal
4
to output an L-level voltage. Next, suppose the L-level voltage is output from the driver
6
. In such a case, if the interconnect
3
is connected normally, then the L-level voltage is transmitted to the terminal
4
and the logic circuit
51
receives and inverts the L-level voltage at the terminal
4
to output an H-level voltage.
Since the inverter is used as the logic circuit
51
in the example shown in
FIG. 7
, the connectivity of the interconnect
3
can be checked by seeing whether or not the output of the logic circuit
51
is opposite to that of the driver
6
. However, suppose the interconnect
3
is not connected normally (e.g., the interconnect
3
is short-circuited with the power supply). In such a situation, even if the L-level voltage has been output from the driver
6
, the logic circuit
51
outputs an L-level voltage, because the potential at the terminal
4
is fixed at the supply potential. That is to say, since the output of the logic circuit
51
is not opposite to that of the driver
6
, it is determined that the interconnect
3
is not connected normally. Also, suppose the interconnect
3
is short-circuited with the ground. In such a situation, even if the H-level voltage has been output from the driver
6
, the logic circuit
51
outputs an H-level voltage, because the potential at the terminal
4
is fixed at the ground potential. That is to say, since the output of the logic circuit
51
is not opposite to that of the driver
6
either, it is also determined that the interconnect
3
is not connected normally.
In the prior art test system, however, the connectivity of the interconnect cannot always be tested correctly.
For example, suppose the interconnect
3
is short-circuited with the power supply via a resistor as shown in FIG.
8
(
a
). In such a situation, even if an L-level voltage has been output from the driver
6
, the potential at the terminal
4
might be lower than the input threshold voltage of the logic circuit
51
depending on an impedance ratio between the driver
6
and the resistor. Then, the logic circuit
51
outputs an H-level voltage, which is opposite to the output voltage of the driver
6
, and it is determined by mistake that the interconnect
3
is connected normally. That is to say, the short-circuited between the interconnect
3
and the power supply cannot be detected in such a case.
The same statement is also true of a situation where the interconnect
3
is short-circuited with the ground via a resistor as shown in FIG.
8
(
b
). In this case, even if an H-level voltage has been output from the driver
6
, the potential at the terminal
4
might be higher than the input threshold voltage of the logic circuit
51
depending on an impedance ratio between the driver
6
and the resistor. Then, the logic circuit
51
outputs an L-level voltage, which is opposite to the output voltage of the driver
6
, and it is also determined by mistake that the interconnect
3
is connected normally. That is to say, the short-circuited between the interconnect
3
and the ground cannot be detected, either.
Furthermore, suppose the interconnect
3
has been disconnected as shown in FIG.
8
(
c
) and there is coupled capacitance between the disconnected interconnect
3
and a second interconnect (not shown). In such a situation, the potential at the terminal
4
is affected by the potential on the second interconnect and therefore, is inconstant and variable. Thus, if the potential on the second interconnect changes in the same way as the output voltage of the driver
6
, then it is determined by mistake that the interconnect
3
is connected normally. This is because the potential at the terminal
4
is affected by the potential variation on the second interconnect. That is to say, the disconnection cannot be detected.
In addition, the prior art test system dissipates power for nothing during normal operation even though no test is being carried out. For example, during normal operation, an analog signal may pass through the interconnect
3
and therefore the potential at the terminal
4
often reaches an intermediate potential close to the input threshold voltage of the logic circuit
51
. As a result, current frequently flows through the logic circuit
51
, thus unnecessarily increasing power dissipation during the normal operation.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to test an analog boundary scan-compliant integrated circuit system more reliably. A more specific object of the present invention is to reduce power dissipation during the normal operation of the system.
Specifically, an inventive integrated circuit system with analog boundary scan capabilities includes: first and second integrated circuits; and an interconnect provided between the first and second integrated circuits to connect these circuits together. The first integrated circuit includes: a terminal to which the interconnect is connected; and multiple logic circuits with mutually different input threshold voltages. Each said logic circuit detects a logical level of a potential at the terminal to carry out a test of whether the interconnect is connected normally.
According to the present invention, the logical level of
Gion Masahiro
Hirose Masaya
Dooley Matthew C.
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
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