Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2006-09-26
2006-09-26
Peugh, Brian R. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S131000, C711S151000
Reexamination Certificate
active
07114041
ABSTRACT:
A circuit generally comprising a command buffer and a read buffer is disclosed. The command buffer may be configured to (i) buffer a plurality of read commands received by the circuit, wherein each read command has one of a plurality of port values and one of a plurality of identification values and (ii) transmit a tag signal from the circuit in response to servicing a particular read command of the read commands. The tag signal may have a particular port value of the port values and a particular identification value of the identification values as determined by the particular read command. The read buffer may be configured to transmit a read signal within a plurality of first transfers from the circuit in response to servicing the particular read command.
REFERENCES:
patent: 6799304 (2004-09-01), Hammitt et al.
patent: 2004/0064646 (2004-04-01), Emerson et al.
patent: 2004/0123036 (2004-06-01), Hammitt et al.
patent: 2004/0123038 (2004-06-01), Shami et al.
Emerson Steven M.
Hammitt Gregory F.
Nystuen John M.
LSI Logic Corporation
Maiorana P.C. Christopher P.
Peugh Brian R.
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