Aluminum disposable spacer to reduce mask count in CMOS...

Details Aluminum disposable spacer to reduce mask count in CMOS... Aluminum disposable spacer to reduce mask count in CMOS...

1999-05-05

2001-07-24

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S301000, C438S302000, C438S303000

Reexamination Certificate

active

06265253

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device on a semiconductor substrate. The invention has particular applicability in manufacturing a plurality of semiconductor devices of different conductivity types on a single substrate.
BACKGROUND ART
Metal oxide semiconductor (MOS) devices typically comprise a pair of ion implanted source/drain regions in a semiconductor substrate, a channel region separating the source/drain regions, and a thin gate oxide and a conductive gate comprising polysilicon or other conductive material formed above the channel region. In a typical integrated circuit, a plurality of MOS devices of different conductivity types, such as n-type and p-type, are formed on a common substrate.
A traditional approach to forming MOS devices of different conductivity types on a single substrate is illustrated in
FIGS. 1A-1G
. As shown in
FIG. 1A
, field oxide areas
115
are formed, as by local oxidation of silicon (LOCOS) or shallow trench isolation (STI), in semiconductor substrate
100
, then a thin gate oxide
105
is thermally grown, and conductive gates
110
, such as polysilicon, are formed. A photoresist mask M
1
is thereafter formed on the areas to be subsequently implanted with p-type impurities, and substrate
100
is implanted, as by ion implantation, with n-type impurities NLDD to form lightly or moderately doped regions
120
, also called “shallow source/drain extensions” (see FIG.
1
B). Adverting to
FIG. 1C
, mask M
1
is then removed, and the areas previously implanted with impurities NLDD are masked with photoresist mask M
2
. Substrate
100
is thereafter implanted, as by ion implantation, with p-type impurities PLDD to form lightly or moderately doped regions
125
.
Next, as shown in
FIG. 1D
, sidewall spacers
130
are formed on the side surfaces of the gates
110
. as by depositing a blanket layer of a dielectric material, such as silicon nitride, and anisotropically etching. A photoresist mask M
3
is thereafter formed on the regions implanted with p-type impurities (see FIG.
1
E), and substrate
100
is implanted, as by ion implantation, with n-type impurities NS/D to form source/drain regions
135
, which include lightly or moderately doped regions
120
. Adverting to
FIG. 1F
, mask M
3
is then removed, and the areas previously implanted with impurities NS/D are masked with photoresist mask M
4
. Substrate
100
is thereafter implanted, as by ion implantation, with p-type impurities PS/D to form source/drain regions
140
. Mask M
4
is then removed, leaving the structure shown in FIG.
1
G.
Source/drain implants NS/D, PS/D are typically implanted at a higher energy and dosage than lightly or moderately doped implants NLDD, PLDD, so source/drain implants NS/D, PS/D penetrate deeper into substrate
100
than lightly or moderately doped implants NLDD, PLDD. Additionally, sidewall spacers
130
prevent moderate or heavy source/drain implants NS/D, PS/D from entering substrate
100
adjacent to or under gates
110
to obtain the desired device performance characteristics. Thus, source/drain regions
135
,
140
have a step corresponding to spacer
130
.
Disadvantageously, the above-described methodology employs four photoresist masks (M
1
-M
4
), each of which requires the steps of spinning on the photoresist, exposing it with a stepper, developing the photoresist, and stripping off the mask after ion implantation. Each of these steps adds to the cost of the semiconductor device and decreases manufacturing throughput, and also subjects the device to additional handling, thereby increasing the likelihood of defects.
Moreover, masks M
1
-M
4
are all “critical masks”; i.e., extremely complex and difficult to design and use. The large number of fine features required to form the masks challenge the capabilities of the photolithographic process necessary to implement them, thereby increasing manufacturing costs and reducing production throughput. As design rules are reduced to 0.18 &mgr;m and under; e.g., 0.15 &mgr;m and under, to meet increasing demands for miniaturization and higher circuit density, shrinking feature sizes cause masks such as M
1
-M
4
to become even more difficult and costly to design and use.
Copending U.S. patent applications Ser. No. 09/271,290, Ser. No. 09/277,161 and Ser. No. 09/268,713 disclose methodology for manufacturing MOS semiconductor devices with a reduced number of critical masks wherein conductive gates are formed on the main surface of a semiconductor substrate, and disposable sidewall spacers are formed on side surfaces of the gates. A mask is then formed on some of the gates, the mask extending onto the main surface adjacent to those gates to cover intended source/drain regions to be implanted with impurities of a first conductivity type.
Moderate or heavy source/drain implants of a second impurity type are thereafter formed in the substrate, as by ion implantation, adjacent to the unmasked gates. The disposable sidewall spacers on the unmasked gates are then removed, and lightly or moderately doped source/drain extension implants of the second impurity type are formed in the substrate, as by ion implantation. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates, the mask extending onto the main surface to cover the previous source/drain implants. Moderate or heavy source/drain implants with impurities of the first conductivity type are then formed, the remaining disposable sidewall spacers are removed, and lightly or moderately doped source/drain extension implants of the first conductivity type formed. The substrate is thereafter heated to diffuse and electrically activate the implants, thereby forming source/drain regions in the substrate.
By reversing the lightly or moderately doped source/drain extension and moderate or heavy source/drain implantation sequence of conventional MOS formation methodologies and employing disposable spacers, the methodologies of the copending applications reduce the critical masking steps from four to two. However, since the disposable spacers are removed during the transistor formation process, another spacer must be formed on the gate sidewalls if silicided contacts are to be formed on the source/drain regions and the gate. Moreover, since there are no spacers on the gate sidewalls when the lightly or moderately doped source/drain extension implants are performed, impurities are implanted immediately adjacent to the gate, and diffuse under the gate when the substrate is heated to form the source/drain junctions. For optimal transistor performance, the source/drain junctions are typically located proximal to, but not under, the gate edges. Thus, the methodologies of the copending applications result in source/drain junction placement that adversely affects the electrical characteristics of the finished device.
Accordingly, there exists a need for a method of manufacturing MOS semiconductor devices with a reduced number of critical masks while avoiding degradations of device performance.
SUMMARY OF THE INVENTION
An advantage of the present invention is a method of forming a plurality of MOS devices of different conductivity types on a common substrate using a minimal number of critical masks, thereby reducing manufacturing costs and increasing production throughput, which method enables optimization of the location of the source/drain junctions of the finished device.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, which method comprises forming first and seco

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