Aluminum/copper clad interconnect layer for VLSI applications

Details Aluminum/copper clad interconnect layer for VLSI applications Aluminum/copper clad interconnect layer for VLSI applications

2002-08-16

2004-08-17

Gurley, Lynne A. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S618000, C438S622000, C438S627000, C438S629000, C438S643000, C438S653000, C438S672000, C438S687000, C438S688000

Reexamination Certificate

active

06777318

ABSTRACT:

BACKGROUND OF THE INVENTION
FIG. 1
schematically illustrates a view of the external wiring scheme of a semiconductor chip
10
. Active bump pads
12
are electrically connected to corresponding wire bond pads
14
by redistribution layer (RDL), or global routing layer, of metal
16
having respective metal lines
18
. A fuse block
20
may also be included in the scheme.
In order to minimize the resistance (IR) drop over a chip, a thick copper (Cu) layer of from about 1 to 3 &mgr;m is used as the global routing layer
16
.
U.S. Pat. No. 4,915,983 to Lake et al. describes a multilayer circuit board fabrication process.
U.S. Pat. No. 4,853,491 to Butt describes a chip carrier for mounting a semiconductor chip.
U.S. Pat. No. 5,525,836 to Mennucci describes a multilayer metal leadframe comprising copper (Cu) or a copper alloy.
SUMMARY OF THE INVENTION
Accordingly, it is an object of one or more embodiments of the present invention to provide an improved method of fabricating global routing layers.
It is another object of one or more embodiments of the present invention to provide an improved, lower cost method of fabricating global routing layers.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate is provided having an overlying patterned dielectric layer. The patterned dielectric layer having at least one lower opening. The at least one lower opening is lined with a first barrier layer. At least one planarized copper portion is formed within the at least one first barrier layer lined lower opening. A patterned layer is formed over the at least one planarized copper portion and the patterned dielectric layer. The patterned layer has at least one upper opening exposing at least a portion of the at least one planarized copper portion. The at least one upper opening is lined with a second barrier layer. At least one aluminum portion is formed within the at least one second barrier layer lined opening to form the at least one aluminum/copper clad interconnect.


REFERENCES:
patent: 4853491 (1989-08-01), Butt
patent: 4915983 (1990-04-01), Lake et al.
patent: 5525836 (1996-06-01), Mennucci
patent: 5767012 (1998-06-01), Fulford, Jr. et al.
patent: 5981374 (1999-11-01), Dalal et al.
patent: 6075711 (2000-06-01), Brown et al.
patent: 6133139 (2000-10-01), Dalal et al.
patent: 6174742 (2001-01-01), Sudhindranath et al.
patent: 6400575 (2002-06-01), Brown et al.
patent: 6413848 (2002-07-01), Giust et al.
patent: 6614091 (2003-09-01), Downey et al.
patent: 2002/0037642 (2002-03-01), Wake et al.
patent: 2003/0173667 (2003-09-01), Yong et al.

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