Alternatively addressed semiconductor memory array

Details Alternatively addressed semiconductor memory array Alternatively addressed semiconductor memory array

1986-04-22

1988-08-09

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365233, G11C 1140

Patent

active

047633026

ABSTRACT:
A memory array and associated control circuitry in which the cells of the array can be accessed according to at least two addressing configurations. A multiple-bit bit address can be applied directly to an address decoder or, responsive to control signals, the bits of the address can be rearranged before being applied to the decoder. Additionally, the width of the accessed word can be increased by optionally ignoring some of the address bits but then increasing the number of bits accessed in parallel.

REFERENCES:
patent: 3800289 (1974-03-01), Batcher
patent: 4056819 (1977-11-01), Lukas
patent: 4494222 (1985-01-01), White et al.
"All Points Addressable Raster Display Memory", Richard Matick, et al., IBM J. Res. Develop., vol. 28, No. 4, Jul., 1984, New York, pp. 379-392.

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