Alternative method for advanced CMOS logic gate etch...

Details Alternative method for advanced CMOS logic gate etch... Alternative method for advanced CMOS logic gate etch...

2011-03-22

2011-03-22

Ahmed, Shamim (Department: 1713)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S689000, C438S702000, C257S369000, C257S407000, C257S412000

Reexamination Certificate

active

07910488

ABSTRACT:
Methods for etching, such as for fabricating a CMOS logic gate are provided herein. In some embodiments, a method of etching includes (a) providing a substrate having a first stack and a second stack disposed thereupon, the first stack comprising a high-k dielectric layer, a metal layer formed over the high-k dielectric layer, and a first polysilicon layer formed over the metal layer, the second stack comprising a second polysilicon layer, wherein the first and second stacks are substantially equal in thickness; (b) simultaneously etching a first feature in the first polysilicon layer and a second feature in the second polysilicon layer until the metal layer in the first stack is exposed; (c) simultaneously etching the metal layer and second polysilicon layer to extend the respective first and second features into the first and second stacks; and (d) etching the high-k dielectric layer.

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