Almost full, almost empty memory system

Details Almost full, almost empty memory system Almost full, almost empty memory system

2005-10-18

2005-10-18

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including signal comparison

C365S189050, C365S189120, C365S221000, C365S233100

Reexamination Certificate

active

06956776

ABSTRACT:
A buffer memory status detection circuit has a binary logic gate (e.g. an OR gate) coupled to a comparator output signal that is asserted when a sum of a first address pointer of a FIFO memory array plus a first offset equals a second address pointer, and to a reset signal. Binary logic provides a binary output (i.e. “0” or “1”) in a first clock domain to two synchronization registers in series that convert the output to a second clock domain. An optional pipeline register improves timing of the output in the second clock domain, and is particularly desirable for use with high-speed clocks.

REFERENCES:
patent: 5506809 (1996-04-01), Csoppenszky et al.
patent: 6097656 (2000-08-01), Kim
patent: 6208703 (2001-03-01), Cavanna et al.
patent: 6337809 (2002-01-01), Kim et al.

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