Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2004-12-07
2008-10-14
Fourson, George R. (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S627000, C438S628000, C438S629000, C438S639000, C438S643000, C438S644000, C438S648000, C438S650000, C438S682000, C438S686000, C257SE23157, C257SE23163, C257SE21584, C257SE21591, C257SE21579
Reexamination Certificate
active
07435679
ABSTRACT:
Apparatus and methods of fabricating a microelectronic interconnect having an underlayer which acts as both a barrier layer and a seed layer. The underlayer is formed by co-depositing a noble metal and a barrier material, such as a refractory metal, or formed during thermal post-treatment, such as thermal annealing, conducted after two separately depositing the noble metal and the barrier material, which are substantially soluble in one another. The use of a barrier material within the underlayer prevents the electromigration of the interconnect conductive material and the use of noble material within the underlayer allows for the direct plating of the interconnect conductive material.
REFERENCES:
patent: 6294836 (2001-09-01), Paranjpe et al.
patent: 6541860 (2003-04-01), Woo et al.
patent: 2002/0006468 (2002-01-01), Paranjpe et al.
patent: 2004/0084773 (2004-05-01), Johnston et al.
PCT Application No. PCT/US2005/044699,International Search Report and Written Opinion, mailed Jun. 9, 2006, 11 pages.
Dominguez Juan E.
Johnston Steven W.
Fourson George R.
Intel Corporation
Maldonado Julio J.
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