Allocation of combined or separate data and control planes

Details Allocation of combined or separate data and control planes Allocation of combined or separate data and control planes

2008-09-09

2008-09-09

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

10789187

ABSTRACT:
A dual mesh interconnect network in a heterogeneous configurable circuit may be allocated between data communication and control communication.

REFERENCES:
patent: 5128871 (1992-07-01), Schmitz
patent: 5848096 (1998-12-01), Shou et al.
patent: 5987490 (1999-11-01), Alidina et al.
patent: 6038386 (2000-03-01), Jain
patent: 6112023 (2000-08-01), Dave et al.
patent: 6195788 (2001-02-01), Leaver et al.
patent: 6226735 (2001-05-01), Mirsky
patent: 6237054 (2001-05-01), Freitag, Jr.
patent: 6260055 (2001-07-01), Sugeno et al.
patent: 6266797 (2001-07-01), Godfrey et al.
patent: 6272188 (2001-08-01), Mobin et al.
patent: 6298319 (2001-10-01), Heile et al.
patent: 6397240 (2002-05-01), Fernando et al.
patent: 6665725 (2003-12-01), Dietz et al.
patent: 6820102 (2004-11-01), Aldrich et al.
patent: 6839751 (2005-01-01), Dietz et al.
patent: 6915502 (2005-07-01), Schott et al.
patent: 6941538 (2005-09-01), Hwang et al.
patent: 7039919 (2006-05-01), Hunt
patent: 7072382 (2006-07-01), Dent
patent: 7073159 (2006-07-01), Tsai et al.
patent: 7119576 (2006-10-01), Langhammer et al.
patent: 7200837 (2007-04-01), Stevens
patent: 2002/0073380 (2002-06-01), Cooke et al.
patent: 2003/0105799 (2003-06-01), Khan et al.
patent: 2004/0006584 (2004-01-01), Vandeweerd
patent: 2004/0090964 (2004-05-01), Reed et al.
patent: 2004/0095907 (2004-05-01), Agee et al.
patent: 2004/0172476 (2004-09-01), Chapweske
patent: 2004/0187088 (2004-09-01), Cambonie
patent: 2004/0194048 (2004-09-01), Arnold
patent: 2004/0250046 (2004-12-01), Gonzalez et al.
patent: 2004/0258069 (2004-12-01), Serbest et al.
patent: 2005/0025222 (2005-02-01), Underbrink et al.
patent: 2005/0138323 (2005-06-01), Synder
patent: 2005/0149890 (2005-07-01), Tsai et al.
patent: 2005/0187998 (2005-08-01), Zheng et al.
patent: 2005/0203988 (2005-09-01), Nollet et al.
patent: 2005/0223110 (2005-10-01), Honary et al.
patent: 2005/0229139 (2005-10-01), Tsai et al.
patent: 2005/0229140 (2005-10-01), Tsai et al.
patent: 1311073 (2003-05-01), None
patent: 2003-244249 (2003-08-01), None
patent: WO-2005094016 (2005-10-01), None
patent: WO-2005094016 (2005-10-01), None
International Search Report and Written Opinion of the International Searching Authority; Dated Oct. 7, 2005; PCT/US2005/010135, (14 pgs).
Albanesi, M. G., et al., “A VLSI 128-Processor Chip for Multiresolution Image Processing”,Proceedings of the First International Conference on Ischia, (May 2, 1994),296-307.
Hui, Z , et al., “Interconnect Architecture Exploration for Low-Energy Reconfigurable Single-Chip DSPs”, VLSI, 99, Proceedings, IEEE Computer Society Workshop on Orlando, FL, (Apr. 8, 1999),2-8.
Marescaux, T. , et al., “Networks on Chip as Hardware Components of an OS for Reconfigurable Systems”,Field-Programmable Logic and Applications, 13th International Conference, vol. 2778, (2003),595-605.
Benini, L. , et al., “System-Level Power Optimization: Techniques and Tools”,ACM Transactions on Design Automation of Electronic Systems, 5(2), (Apr. 2000),115-192 Pgs.

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