All dual damascene oxide etch process steps in one confined...

Details All dual damascene oxide etch process steps in one confined... All dual damascene oxide etch process steps in one confined...

2002-07-31

2003-05-06

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S627000, C438S638000, C438S643000, C438S653000, C438S700000, C438S707000, C438S738000

Reexamination Certificate

active

06559049

ABSTRACT:

BACKGROUND OF THE INVENTION
(A) Field of the Invention
The present invention relates to a semiconductor dual damascene etching process, and more specifically to a semiconductor dual damascene etching process employing a confined plasma chamber.
(B) Description of Related Art
With the increase of integrity for the integrated circuits, the distance between the metal lines of semiconductor devices is becoming smaller. RC delay caused by the resistance of the lines and the capacitance of the dielectric between the lines becomes the main reason of the delay of signal transmission and limits device speed. Therefore, copper (Cu) lines and the intermetal dielectric (IMD) are continuously being improved for the fabrication of deep sub-micron devices to overcome the increase of parasitic resistance and capacitance caused by narrower line width in advanced process.
The dual damascene process is used to replace the current Al—Cu metal line process, a process of Back-End of Line (BEOL) of the wafer manufacturing, which is used after forming the contact plug on the silicon substrate and may be repeated several times based on the designed number of metal line layers of device. Currently, most large semiconductor fabs in the world are investing substantial manpower and capital to develop the dual damascene process. Thus, the performance and stability of the process will significantly influence the competitiveness for each large semiconductor fab.
Because copper line is difficult to be etched by plasma, most of the copper lines are conducted with dual damascene process, in which the etching process has a very important role. The dual damascene etching process may be categorized by various forming sequences of dual damascene structure. FIG.
1
(
a
) to FIG.
1
(
d
) illustrate the most popular dual damascene etching process, in which a via hole is etched first and the other structures are formed afterward. Referring to FIG.
1
(
a
), first of all, IMD
102
,
104
and an etch stop layer
106
of a semiconductor device
10
are etched to form a via hole, i.e. the opening in the IMD
104
, in contact with a barrier layer
108
. A photoresist layer
114
is patterned as a mask for the following trench etching, and the hard mask
116
originally used to define the via hole exposed to the opening of the photoresist layer
114
is removed. In FIG.
1
(
b
), the IMD
102
is etched until the etch stop layer
106
is reached to form a trench, i.e. the opening in the intermetal dielectric
102
. In FIG.
1
(
c
), the photoresist layer
114
is removed. In FIG.
1
(
d
), the barrier layer
108
and the hard mask
116
are etched, inducing the via hole to be in contact with the metal line
112
under the barrier layer
108
, and finally the dual damascene structure is completed.
Another dual damascene process shown in FIG.
2
(
a
) to FIG.
2
(
d
) is to form trenches first and then to conduct the following processes. Referring to FIG.
2
(
a
), firstly, a semiconductor device
20
with a trench is provided, which comprises IMD
202
,
204
, an etch stop layer
206
, a barrier layer
208
, a metal line
212
, and a photoresist layer
214
, wherein the opening of the IMD
202
is a trench, and the opening in the photoresist layer
214
is for via hole etching. In FIG.
2
(
b
), the etch stop layer
206
and the IMD
204
are etched until the barrier layer
208
is reached to form a via hole. In FIG.
2
(
c
), the photoresist layer
214
is removed, and a hard mask
216
is formed as a mask for removing the barrier layer
208
. In FIG.
2
(
d
), the barrier layer
208
and the hard mask
216
are etched, and then the dual damascene structure is formed.
Besides the dual damascene processes mentioned above, a method that does not need the etch stop layers
106
,
206
is shown in FIG.
3
(
a
) to FIG.
3
(
e
). Referring to FIG.
3
(
a
), a semiconductor device
30
comprises an IMD
302
, a barrier layer
304
, a metal line
306
, a hard mask
308
and a photoresist layer
312
, wherein the opening in the IMD
302
is a via hole. In FIG.
3
(
b
), the hard mask
308
is etched to define the pattern required by the trench. In FIG.
3
(
c
), the IMD
302
is etched and stopped in the middle of the IMD
302
to form a trench in the upper portion of the IMD
302
. In FIG.
3
(
d
), the photoresist layer
312
is removed. In FIG.
3
(
e
), the barrier layer
304
and the hard mask
308
are etched so that the via hole is in contact with the metal line
306
.
Most conventional etching chambers employ “polymerized mode” or “dirty mode” during wafer processing, i.e. a polymer layer is deposited on the inner wall surface of the chamber prior to etching. Thus, the polymer layer can prevent the plasma contacting the inner wall of the chamber, so metal contamination from the inner wall can be avoided. In addition, high selectivity for the photoresist can be achieved. Because most of the photoresist in mass production is an organic substance, conventional methods employ a photoresist stripper with oxygen or oxygen plasma, or a mixture solution of thermal sulfuric acid and dioxide water to remove the photoresist. If oxygen plasma is used for photoresist stripping in the etching chamber, the polymer layer will be removed as well. Thus, the above-mentioned processing steps, such as via hole or trench etching, photoresist stripping, barrier layer etching and hard mask removal cannot be performed in the same etching chamber, and have to be conducted respectively in different tools. Normally, the etching process is conducted in vacuum, thus if a wafer have to change the tool, chamber venting, wafer transferring between different tools, chamber pumping and robot moving and wafer standby would cost much time and affect the production throughput.
SUMMARY OF THE INVENTION
The semiconductor dual damascene process in accordance with the present invention in a confined plasma chamber can integrate all the above-mentioned process steps as a continuous procedure, so as to effectively reduce the process time and manufacturing cost. Moreover, the dual damascene process of the present invention is under clean mode, reducing the process instability caused by the “memory effect” of polymerized mode. Therefore, the dual damascene process in accordance with the present invention can mix-run in the same chamber. Also, because there is no polymer residue in the confined plasma chamber, the number of particle and the likelihood of particle occurrence can be minimized so that preventive maintenance (PM) period of the chamber can be extended.
The semiconductor dual damascene etching process of the present invention is applied in a confined plasma chamber, the confined plasma chamber comprising a confinement ring surrounding a wafer, and an anti-etching upper electrode plate. The semiconductor dual damascene etching process comprises the steps of etching at least one IMD layer, stripping a photoresist layer and etching a barrier layer. These steps are all continuously conducted under clean mode in the confined plasma chamber, so that other tools are not needed and the capitals of tool investment can be effectively reduced.
The confinement ring is made of quartz to prevent the inner wall of the chamber from being bombarded by plasma. The upper electrode plate is made of silicon. The quartz is a composition of SiO
2
, and a normal dielectric layer is a SiO
2
also but with a different structure. Thus, during etching, the quartz confinement ring will generate volatile gas, such as CO and SiF
4
, etc., and the quartz ring is likely to release the oxygen in the SiO
2
material, so as to effectively avoid polymer deposition. The C—F based gases usually used in the dielectric etching are provided with relatively high selectivity to silicon, i.e. with very slow etching rate for silicon. Thus, the upper electrode plate is not easily damaged during etching. Moreover, the silicon plate may provide the function of combining the fluoride in the plasma to increase the selectivity during etching.
The present invention can also be applied in a wafer including a s

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