Alignment of trench for MOS

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S300000, C257SE29118, C257SE29131, C257SE29262, C257SE21410, C257SE21629, C257SE21652, C257SE21653

Reexamination Certificate

active

07608510

ABSTRACT:
Manufacturing a power transistor by forming a gate structure on a first layer, forming a trench in the first layer, self aligned with the gate structure, and forming part of the transistor in the trench. By forming a spacer next to the gate, the spacer and gate can be used as a mask when forming the trench, to allow space for a source region next to the gate. The self-aligning rather than forming the gate after the trench means the alignment is more accurate, allowing size reduction. Another aspect involves forming a trench in a first layer, filling the trench, forming a second layer on either side of the trench with lateral overgrowth over the trench, and forming a source region in the second layer to overlap the trench. This overlap can enable the chip area to be reduced.

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